Lead Frame Die Pad Openings for Multichip Package Reliability
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Solution Overview
Problem
Conventional multichip packages face challenges in accommodating larger semiconductor chips without increasing package size, leading to weakened adhesion between the die pad and substrate, potential distortion, and compromised reliability and performance.
Innovation Solution
A lead frame with a die pad featuring openings that expose electrode pads on the substrate, allowing for a larger semiconductor chip mounting area while maintaining the package size, ensuring strong adhesion and minimizing the die pad's area expansion, thus enhancing reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the exclusively-possessed area of each opening at the die pad is made greater to accommodate larger semiconductor chips, then the capacity of the multichip package is increased, but the bonding or adhesion area between the die pad and substrate becomes insufficient, weakening the junction strength and impairing reliability
Solution Approach 1:
The die pad is segmented into multiple functional zones: a substrate mounting area for bonding to the substrate, a chip mounting area for securing semiconductor chips, and openings for wire bonding. This segmentation allows each area to be optimized independently, enabling larger chip capacity while preserving sufficient substrate bonding area.
Solution Approach 2:
The invention utilizes the vertical dimension by providing openings that penetrate through the die pad thickness. This allows electrode pads on the substrate to be exposed through the openings for wire bonding, effectively adding a third dimension to the mounting configuration without reducing the planar substrate bonding area.
2Quantity of substance
If the exclusively-possessed area of each opening at the die pad is made greater to accommodate larger semiconductor chips, then the capacity of the multichip package is increased, but the entire die pad volume must be increased, leading to an increase in package size
Solution Approach 1:
The die pad is divided into distinct functional regions that allow efficient space utilization. The substrate mounting area, chip mounting area, and openings are segmented to maximize capacity within the existing die pad volume without requiring overall package enlargement.
3Quantity of substance
If the exclusively-possessed area of each opening at the die pad is made greater without expanding the flat size of the die pad, then the capacity is increased, but the strength of the die pad itself becomes insufficient, causing distortion and deformation during manufacturing
Solution Approach 1:
The die pad structure is segmented into reinforced areas (substrate mounting area and chip mounting area) and opening areas. This segmentation allows the solid portions to maintain structural strength while the openings provide access for wire bonding, preventing distortion during manufacturing.
Solution Approach 2:
Different regions of the die pad are given different properties: the substrate mounting area and chip mounting area maintain solid structure for strength, while the openings provide local access points. This local differentiation allows capacity increase without compromising overall die pad strength.
4Quantity of substance
If the bonding or adhesion area is reduced to accommodate larger chips, then the chip size and capacity are increased, but the reliability of the package is impaired due to insufficient bonding strength
Solution Approach 1:
The die pad is segmented to separate substrate bonding functions from chip mounting functions. This allows the substrate mounting area to be optimized for adhesion strength while the chip mounting area and openings accommodate larger chips and wire bonding operations.
Data Source
AI summary
The present invention provides a semiconductor device which comprises a lead frame including a die pad having one or two or more openings, a substrate mounted over the die pad so as to expose a plurality of semiconductor chip connecting second electrode pads from the openings of the die pad, a plurality of semiconductor chips mounted over the die pad and the substrate, bonding wires that connect chip electrode pads of the semiconductor chip and their corresponding semiconductor chip connecting first and second electrode pads of the substrate, and a sealing portion which covers these and is provided so as to expose parts of leads.