Lead Frame Grooves and Electroplating for Soldering
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Solution Overview
Problem
The soldering performance of semiconductor chip package devices is undesirable due to the limited area available for soldering, as the distance between adjacent pins becomes smaller and pin density increases, making it challenging to achieve reliable soldering.
Innovation Solution
A semiconductor chip package device and method that include a lead frame with specific grooves and an electroplating layer, where the lead frame has first, second, and third grooves forming through holes and extending into edges, and an electroplating layer covering these grooves to enhance soldering performance by providing additional areas for solder climbing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pin density is increased and distance between adjacent pins is reduced, then device integration is improved, but soldering performance deteriorates due to limited solder climbing area
Solution Approach 1:
The patent introduces grooves with different depths (first grooves, second grooves, third grooves) to create multi-level structures on the lead frame. This transforms the traditional two-dimensional solder climbing surface into a three-dimensional multi-level structure, providing additional solder climbing areas without increasing the planar pin density. The electroplating layer is formed on these multi-level groove structures to create extended solderable surfaces.
Solution Approach 2:
The lead frame surface is segmented into multiple grooves (first grooves extending from first surface to second surface, second grooves extending from second surface to first surface, third grooves at edges) that divide the solder climbing area into distinct sections. This segmentation creates multiple independent solder climbing paths and areas, allowing solder to climb up different groove structures rather than relying on a single limited flat surface.
2Productivity
If pin density is increased, then device performance is improved, but the area available for soldering decreases
Solution Approach 1:
By creating grooves with varying depths and combining them with an electroplating layer, the patent extends the solder climbing area vertically rather than horizontally. The first grooves, second grooves, and third grooves create multi-level surfaces that increase the effective soldering area without occupying additional planar space, thus maintaining high pin density while providing sufficient solder climbing area.
Solution Approach 2:
The electroplating layer is formed within and on the grooves created in the lead frame, creating a nested structure where the electroplating material fills and extends from the groove structures. This nesting approach maximizes the use of available space by utilizing the vertical volume of the grooves to create additional solder climbing surfaces.
3Reliability
If grooves are formed to increase solder climbing area, then soldering performance is improved, but device complexity increases
Solution Approach 1:
The lead frame is segmented into multiple groove types (first grooves, second grooves, third grooves) with specific configurations. The first grooves extend from the first surface to the second surface, the second grooves extend from the second surface to the first surface, and the third grooves are disposed at edges. This segmented groove structure provides systematic solder climbing paths while maintaining manufacturing feasibility through standardized groove formation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves soldering performance and increases the production yield of semiconductor chip package devices by providing additional areas for solder climbing, preventing pin bending and dropping, and enhancing the structural strength of the lead frame.
Implementation Method 1
forming an electroplating layer on the second surface of the metal plate
Data Source
AI summary
Semiconductor chip package device and semiconductor chip package method are provided. The semiconductor chip package device includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves disposed at ends of the lead frame. The chips are electrically connected to the lead frame. The encapsulating layer is formed by using an encapsulating material to encapsulate the chips and at least a portion of the lead frame. The first grooves are filled with the encapsulating material. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.