Lead-Frame Half-Bridge Package Reducing Parasitic Inductance
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Solution Overview
Problem
Packaged half-bridge circuits introduce unwanted resistance and inductance due to external or internal interconnections between transistors, complicating manufacturing and limiting on-resistance performance due to die size constraints within a given package footprint.
Innovation Solution
A lead-frame based half-bridge package design where the second contact element acts as both a die pad and a clip for the source terminal, eliminating the need for a bridge connection and allowing for stacked die configuration, reducing parasitic resistance and inductance, and enabling larger die sizes within the same package footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external or internal interconnections are used between transistors, then the half-bridge circuit can be packaged, but unwanted resistance and inductance are introduced
Solution Approach 1:
The patent merges the die pad and the interconnection structure into a single integrated component. The interconnection is formed as an extension of the die pad itself, eliminating the need for separate bridge connections. This integration reduces the number of discrete components and interfaces, thereby minimizing parasitic resistance and inductance while maintaining reliable electrical connection between the transistors.
Solution Approach 2:
The patent introduces a specially designed interconnection structure that acts as an intermediary element with optimized electrical properties. This interconnection is specifically engineered to minimize parasitic effects while providing robust electrical coupling between the transistors, serving as a mediator that reduces harmful electrical characteristics rather than simply transmitting signals.
2Reliability
If bridge connection is used to connect transistors, then electrical connection is achieved, but manufacturing alignment becomes complicated
Solution Approach 1:
By merging the die pad and interconnection into a single monolithic structure, the patent eliminates the need for separate alignment steps between discrete components. The interconnection is formed as an integral part of the die pad, ensuring automatic alignment and eliminating complex manufacturing alignment requirements while maintaining reliable electrical connection.
Solution Approach 2:
The interconnection structure is pre-formed as part of the die pad fabrication process before the transistors are mounted. This preliminary formation of the interconnection ensures that the electrical pathway is established with precise geometry and minimal parasitics, eliminating the need for subsequent alignment operations and simplifying the overall manufacturing process.
3Area of stationary object
If standard package footprint is used, then package size is constrained, but die size is limited thereby limiting on-resistance performance
Solution Approach 1:
The patent utilizes three-dimensional stacking of semiconductor dies vertically above each other, transitioning from a two-dimensional layout to a three-dimensional configuration. This vertical arrangement allows larger effective die area for power handling and lower on-resistance within the same package footprint, as the die are stacked in the vertical dimension rather than spread out horizontally.
Solution Approach 2:
The patent employs a nested configuration where one semiconductor die is positioned directly above another, with the interconnection structure serving as both the die pad for the upper die and the connection element to the lower die. This nesting arrangement maximizes the use of available package volume and allows larger effective die sizes without increasing the package footprint.
Data Source
AI summary
A lead-frame based packaged half-bridge circuit is provided that is useful in power electronics applications, such as DC-DC converters and motor controllers. The circuit reduces or eliminates unwanted additional resistance and inductance produced from interconnections that degrade performance in typical packaged half-bridge circuits.