Lead Frame Semiconductor Package for Heat Dissipation and Low Inductance
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Solution Overview
Problem
Existing semiconductor device packages have poor heat dissipation characteristics and increased costs and process times due to multiple wiring processes.
Innovation Solution
A semiconductor device package with a horizontal channel structure semiconductor device, a lead frame with conductive members bonded to electrode pads, and a mold covering the conductive members and semiconductor device to enhance heat dissipation and reduce parasitic inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal wiring is used to connect electrodes to lead frames, then electrical connections are established, but heat dissipation characteristics deteriorate and parasitic inductance increases
Solution Approach 1:
The patent removes the metal wiring layer from the package structure, directly bonding the lead frame to the semiconductor device electrodes. This extraction of the intermediate wiring layer eliminates the source of parasitic inductance and improves heat dissipation pathways, resolving the contradiction between electrical connection reliability and heat dissipation performance.
Solution Approach 2:
Instead of using metal wiring to connect electrodes to lead frames (traditional approach), the patent inverts the connection method by directly bonding the lead frame to the electrodes. This inversion eliminates the wiring process entirely, reducing parasitic inductance and simplifying the manufacturing process while maintaining electrical connectivity.
2Reliability
If multiple wiring processes are performed to connect electrodes, then electrical connections are achieved, but manufacturing costs and process time increase
Solution Approach 1:
The patent extracts and eliminates the complex multi-step wiring process from the manufacturing sequence. By directly bonding the lead frame to the semiconductor device electrodes, it removes numerous fabrication steps including metal deposition, patterning, and wiring assembly, thereby significantly reducing manufacturing time and costs while maintaining reliable electrical connections.
Solution Approach 2:
The patent merges the electrical connection function and mechanical support function into a single direct bonding step between the lead frame and electrodes. This consolidation eliminates the need for separate wiring processes, reducing both manufacturing complexity and process time while ensuring reliable electrical connectivity.
3Reliability
If a traditional wiring structure is used, then electrode connections are established, but heat generated from the semiconductor device cannot be effectively dissipated
Solution Approach 1:
The patent removes the metal wiring layer that acted as a thermal barrier between the semiconductor device and the heat dissipation path. By directly bonding the lead frame to the electrodes, it creates an uninterrupted thermal pathway that allows heat to be efficiently conducted away from the device, resolving the contradiction between electrical connection stability and heat dissipation efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively discharges heat generated from the semiconductor device, reduces parasitic inductance, and improves the durability of the semiconductor device package against electrical and mechanical shocks, while also reducing processing times and costs.
Implementation Method 1
heat generated from a semiconductor device may be dissipated to the outside through metal wires, a mold, and a silicon substrate
Implementation Method 2
a lead frame including a plurality of conductive members bonded to the plurality of electrode pads
Data Source
AI summary
Provided are a semiconductor device package and/or a method of fabricating the semiconductor device package. The semiconductor device package may include a semiconductor device including a plurality of electrode pads on an upper surface of the semiconductor device, a lead frame including a plurality of conductive members bonded to the plurality of electrode pads, and a mold between the plurality of conductive members.