Lead Frame Chip Mounting With Insulated Wires for Compact Power Packages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in reducing size while maintaining high current density, low loss, and high heat dissipation, particularly due to issues with insulation reliability and voltage withstand in power semiconductor applications.
Innovation Solution
The semiconductor device design incorporates a bed with a semiconductor chip mounted on wires via a joint material and insulating films, where the wires are positioned below the chip, and the insulating films ensure electrical insulation and stability, using materials like silver paste for the joint material and polyimide or solder resist for the insulating films to achieve reliable and compact structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the semiconductor chip size is reduced to decrease device size, then the device size is reduced, but the current density and heat dissipation performance deteriorate
Solution Approach 1:
The patent transitions from planar wire arrangement to a three-dimensional structure where wires are positioned below the chip surface. The chip is mounted on an insulating substrate with wires arranged in a planar pattern on the substrate surface, allowing the chip to extend over multiple wires in the vertical dimension while maintaining compact footprint.
Solution Approach 2:
The patent implements a nested configuration where multiple wires are positioned beneath the chip, with the chip effectively 'nesting' over the wire array. The insulating substrate nests within the overall device structure, providing a foundation that organizes multiple components (chip, wires, substrate) in a compact hierarchical arrangement.
2Reliability
If multiple wires are used below the chip to increase current carrying capacity, then electrical conductivity improves, but device complexity increases
Solution Approach 1:
The insulating substrate serves multiple functions simultaneously: it provides electrical insulation between the chip and wires, provides mechanical support for the wire array, enables thermal management pathways, and facilitates the bonding of multiple wires to the chip. This multi-functionality reduces the need for separate components and simplifies the overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a reduced size semiconductor device with enhanced reliability and insulation, ensuring stable operation under high voltage conditions and maintaining high thermal and electrical conductivity.
Implementation Method 1
a joint material provided between the bed surface and the bottom surface
Implementation Method 2
maintaining high thermal and electrical conductivity
Implementation Method 3
the insulating films ensure electrical insulation and stability
Data Source
AI summary
Provided is a semiconductor device including: a bed having a bed surface; a semiconductor chip having a bottom surface larger than the bed surface, the semiconductor chip being provided such that a center of the bottom surface is disposed above the bed surface and the bottom surface having a first end and a second end; a joint material provided between the bed surface and the bottom surface; a plate-like first wire having a first surface and provided such that the first surface faces the first end; a plate-like second wire having a second surface and provided such that the second surface faces the second end; a first insulating film having a third surface and a fourth surface provided on an opposite side of the third surface, the third surface being in contact with the first end, the fourth surface being in contact with the first surface; and a second insulating film having a fifth surface and a sixth surface provided on an opposite side of the fifth surface, the fifth surface being in contact with the second end, the sixth surface being in contact with the first surface.