Lead Frame with Insulating Fill for Semiconductor Package
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Solution Overview
Problem
Existing semiconductor package manufacturing technologies face challenges in miniaturization and high-integration due to high material costs, strict process control requirements, and increased tack-time, leading to higher product prices and defects.
Innovation Solution
A lead frame and semiconductor package design using a low-cost material with a pre-plating layer and insulating organic material, featuring a Quad Flat Non-leaded (QFN) structure, where the die pad and lead patterns are formed from copper or nickel alloys, and the manufacturing process involves half-etching and back-etching with reduced process control, to minimize electric short circuits and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-priced materials and strict process control are used to achieve fine pitch and fine pattern, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent changes the material parameter from high-priced to low-priced materials while adjusting the etching process parameters (half-etching depth control) to achieve the required fine pitch and fine pattern without strict process control, thereby reducing manufacturing cost while maintaining manufacturing precision
Solution Approach 2:
The patent applies partial etching (half-etching) rather than complete etching, where the etching depth is controlled to stop at a specific depth without penetrating through the entire substrate. This partial action reduces the etching requirements and allows use of lower-cost materials and processes while still achieving the necessary fine pattern definition
2Reliability
If strict process control is implemented to reduce error occurrence, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent performs preliminary half-etching from both upper and lower surfaces before final assembly, pre-defining the etching spaces and reducing the need for strict process control during subsequent operations. This preliminary action ensures proper pattern formation while allowing faster, less controlled final processing steps
Solution Approach 2:
The etching process is segmented into half-etching from the upper surface and half-etching from the lower surface, with each surface etched to a controlled depth that stops before meeting in the middle. This segmentation allows independent control of each etching operation and reduces the cumulative error potential, improving reliability without requiring excessively tight overall process control
3Manufacturing precision
If complete etching is performed to ensure pattern separation, then manufacturing precision is improved, but electric short circuiting increases
Solution Approach 1:
The patent uses partial etching (half-etching) from both surfaces that stops before complete penetration, creating etching spaces that are filled with insulating material. This partial action achieves sufficient pattern separation for manufacturing precision while the insulating fill prevents electric short circuiting that would result from complete etching
Solution Approach 2:
The patent introduces an insulating material as an intermediary substance that fills the etching spaces between the upper and lower surfaces. This intermediary material serves dual purposes: it maintains the pattern separation needed for manufacturing precision while simultaneously preventing electric short circuits between conductive layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables cost-effective mass production of semiconductor packages with reduced manufacturing time and error, ensuring mechanical stability and minimizing electric short circuits, thus improving product reliability and reducing defective products.
Implementation Method 1
an insulating organic material filling etching spaces interposed between the die pad and the lead patterns and structurally supporting the die pad and the lead patterns
Implementation Method 2
a pre-plating layer formed on both upper and lower surfaces of the die pad and the lead patterns
Data Source
AI summary
Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die pad on which a semiconductor chip is installable; a plurality of lead patterns formed around a circumference of the die pad; an insulating organic material filling etching spaces interposed between the die pad and the lead patterns and structurally supporting the die pad and the lead patterns; and a pre-plating layer formed on both upper and lower surfaces of the die pad and the lead patterns.