Lead Frame Bonding Layout for Low-Void Semiconductor Assembly

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Solution Overview

Problem

Void content in the solder used to join planes of a semiconductor device reduces heat dissipation and thermal runaway, leading to a weak structure and reduced reliability.

Innovation Solution

A semiconductor device design with a lead frame structure that includes specific bonding material thickness variations and connector configurations to minimize void formation and enhance heat dissipation, ensuring a wide safe operation area and high reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If solder is used to join planes of MOSFET, then electrical connection is achieved, but void content in solder reduces heat dissipation and creates thermal runaway risk

Engineering Contradiction:
Improvethermal runaway resistanceVSAvoidheat dissipation
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent changes the physical parameters of the bonding material by using a bonding material with different properties than traditional solder, specifically one that can be controlled to have minimal void content and optimized thermal conductivity, thereby improving heat dissipation while maintaining electrical connection

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies different bonding material thicknesses in different regions: a first bonding material portion with first thickness in a first region and a second bonding material portion with second thickness in a second region, optimizing both electrical connection and heat dissipation in different areas of the device

Inventive Principle:
Principle #3Local quality

2Reliability

If uniform bonding material thickness is used, then manufacturing is simplified, but void formation cannot be minimized in critical areas

Engineering Contradiction:
Improvevoid content controlVSAvoidbonding material application
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent implements non-uniform bonding material thickness with different portions having different thicknesses in different regions, allowing void minimization in critical areas while maintaining manufacturability through controlled application processes

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs a face-down bonding process where the semiconductor chip is bonded to the lead frame in an inverted position, which is a preliminary action that prevents void formation in critical areas before final assembly, thereby improving reliability without significantly complicating manufacturing

Inventive Principle:
Principle #10Preliminary action

3Reliability

If thicker bonding material is used, then void content is reduced, but thermal resistivity increases

Engineering Contradiction:
Improvevoid contentVSAvoidthermal resistivity
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent uses different bonding material thicknesses in different regions: thicker in areas where void prevention is critical and thinner in areas where heat dissipation is prioritized, thereby simultaneously achieving both void reduction and low thermal resistivity

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses a bonding material that combines properties of both solder and adhesive, providing a composite solution that offers both mechanical bonding strength and optimized thermal conductivity, allowing thickness optimization without sacrificing either void prevention or heat dissipation

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively minimizes voids, maintaining low thermal resistivity and ensuring a large safe operation area, thereby enhancing the reliability and performance of the semiconductor device.

Implementation Method 1

a first bonding material provided between the first upper surface and the semiconductor chip, the first bonding material joining the first upper surface and the semiconductor chip

Methodology Applied
Scientific EffectAdhesion: Adhesive

Implementation Method 2

maintaining low thermal resistivity and ensuring a large safe operation area, thereby enhancing the reliability and performance

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS12463117B2Semiconductor device
Publication Date: 2025.11.04 KK TOSHIBA
  • US12463117B2 patent drawing
  • US12463117B2 patent drawing
  • US12463117B2 patent drawing

AI summary

A semiconductor of an embodiment includes a lead frame including a first bed; a first post; a second post; a semiconductor chip provided on the first upper surface; a first bonding material provided between the first upper surface and the semiconductor chip, the first bonding material joining the first upper surface and the semiconductor chip, a first film thickness of the first bonding material portion being thinner than a second film thickness of the second bonding material portion; a first connector; a second bonding material; and a third bonding material.