Lead Frame Overlap Insulation Structure for High-Voltage Packaging

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Solution Overview

Problem

In semiconductor devices, the integration of lead frames and bonding wires without adequate sealing can lead to short circuits when a high voltage is applied, as current can flow along the sealing surface between lead frames, compromising the device's rigidity and reliability.

Innovation Solution

A semiconductor device design featuring a wiring unit with a gap between lead frames, where the wiring holding portion includes a wiring gap portion to fill the gap and a wiring surface portion to ensure insulation, preventing current flow between lead frames and maintaining insulation even when exposed to high voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a plurality of lead frames are integrally formed by insert molding without adequate sealing, then device complexity is reduced and ease of manufacture is improved, but reliability deteriorates due to current flow along the sealing surface between lead frames under high voltage

Engineering Contradiction:
Improveease of manufactureVSAvoidreliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

An insulating coating is applied to the sealing surface of the lead frames to act as an intermediary barrier that prevents current flow between adjacent lead frames while maintaining the integral molding structure. This coating layer resolves the contradiction by enabling reliable electrical isolation without requiring separate sealing components or complex manufacturing processes.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If extensive sealing is applied to prevent current flow between lead frames, then reliability is improved, but device complexity increases and ease of manufacture deteriorates

Engineering Contradiction:
ImprovereliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The sealing approach is changed from a structural parameter (physical barriers between lead frames) to a surface property parameter (electrical insulation coating). This parameter change maintains reliability by preventing current flow while significantly reducing device complexity and simplifying manufacturing, as the coating is applied in a single step during the molding process rather than requiring multiple assembly steps.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If lead frames are placed close together to reduce inductance, then productivity is improved, but harmful factors increase due to potential current leakage between adjacent lead frames

Engineering Contradiction:
ImproveproductivityVSAvoidharmful factors
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The insulating coating transforms the potentially harmful effect of close lead frame spacing (current leakage) into a beneficial configuration (reduced inductance). By applying the coating, the lead frames can be placed as close together as possible to minimize inductance and improve productivity, while the coating prevents the harmful current leakage that would otherwise occur at such close spacing.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS11984386B2Semiconductor device
Publication Date: 2024.05.14 FUJI ELECTRIC CO LTD
  • US11984386B2 patent drawing
  • US11984386B2 patent drawing
  • US11984386B2 patent drawing

AI summary

A semiconductor device includes a semiconductor element, a substrate including an insulating board, and first conductive plate and second conductive plate on the insulating board, and a wiring unit including a first lead frame electrically connected to the first conductive plate and having a first wiring portion wired parallel to the insulating board, a second lead frame electrically connected to the second conductive plate, and having a second wiring portion above the first lead frame and overlapping the first wiring portion in a plan view at a superimposed area, a gap between the first and second lead frames being formed in the superimposed area, and a wiring holding portion holding the first and second lead frames. The wiring holding portion includes a wiring gap portion which fills in the gap, and a wiring surface portion disposed over the second wiring portion in the superimposed area.