Semiconductor Lead Frame Plating with Inverted Trapezoid Cross-Section
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Solution Overview
Problem
Conventional semiconductor packages face issues with low adhesive strength of internal terminals, leading to potential terminal drop-out during the etchback process after resin encapsulation, which increases costs and reduces process yield, and makes the packages prone to terminal dislodgment due to external shocks.
Innovation Solution
A semiconductor lead frame design featuring internal-terminal plating layers with an inverted trapezoid cross-sectional shape and external-terminal plating layers without the fall-off prevention structure, where the internal-terminal plating layers are formed with a reverse tapered lateral surface to prevent falling off from the encapsulating resin, and the external-terminal plating layers are formed without this structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If internal terminals are formed with simple plating layers, then manufacturing cost is reduced, but adhesive strength between terminals and encapsulating resin is insufficient causing terminal drop-out during etchback process
Solution Approach 1:
The invention changes the geometric parameters of the plating layer by forming an inverted trapezoid cross-sectional shape with a reverse tapered lateral surface. This parameter change increases the contact area and mechanical interlocking with the encapsulating resin, thereby improving adhesive strength without requiring additional materials or complex manufacturing processes
Solution Approach 2:
Instead of forming a conventional tapered shape that narrows toward the top, the invention uses an inverted trapezoid shape where the plating layer widens toward the top surface. This inverted geometry provides a larger bonding area for the encapsulating resin and prevents terminal drop-out during etchback, resolving the contradiction between simple manufacturing and reliable adhesion
2Manufacturing precision
If etching process is used to form lead frame pattern, then precise pattern formation is achieved, but manufacturing cost increases due to expensive etching solutions and additional process steps
Solution Approach 1:
The invention performs the pattern formation action during the plating process itself by using a plating mask with the desired pattern. The plating layer is deposited directly in the required pattern configuration, eliminating the need for subsequent etching processes. This preliminary pattern formation achieves both precision and cost reduction
3Ease of manufacture
If plating layers are formed on both top surface and back surface, then complete terminal coverage is achieved, but adhesive strength during etchback is insufficient
Solution Approach 1:
The invention applies different geometric qualities to different locations of the plating layer. The plating layer forming the internal terminal has an inverted trapezoid cross-section with reverse tapered lateral surface for maximum adhesion, while other plating layers maintain conventional geometry. This local differentiation ensures adhesive strength where needed without compromising manufacturing efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents terminal fall-off from the encapsulating resin during the etchback process, maintains adhesive strength, and reduces manufacturing costs without the need for expensive etching processes, while ensuring the semiconductor package remains secure against external shocks.
Implementation Method 1
a first plating layer for an internal terminal is provided around the semiconductor chip mounting area
Implementation Method 2
a second plating layer for an external terminal is provided on a back surface of the metal plate
Data Source
AI summary
A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area. A second plating layer for an external terminal is provided on a back surface of the metal plate at a location opposite to the semiconductor chip mounting area. The first plating layer includes a fall-off prevention structure for preventing the first plating layer from falling off from an encapsulating resin when the top surface of the metal plate is encapsulated in the encapsulating resin. The second plating layer does not include the fall-off prevention structure.