Lead Frame Plating Structure for Simpler Semiconductor Packaging
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Solution Overview
Problem
The conventional manufacturing process of semiconductor devices requires multiple plating steps, which complicates the production process.
Innovation Solution
A semiconductor device design involving a first plating layer covering the obverse and reverse surfaces of leads, and a second plating layer exposed from the sealing resin, allowing the manufacturing process to be simplified with only two plating steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If multiple plating steps are performed to form different plating layers on the lead frame, then the bonding strength and adhesion are improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges multiple plating operations into a single plating step by forming a multi-layer plating structure (first plating layer and second plating layer) simultaneously or in sequence during one plating process. This consolidation maintains the functional benefits of multiple plating layers while eliminating the need for separate plating steps, thereby reducing manufacturing process complexity while preserving bonding strength.
Solution Approach 2:
The patent applies preliminary plating treatment to the lead frame before mounting the semiconductor element and forming the sealing resin. By pre-forming the multi-layer plating structure on the lead frame in advance, the subsequent manufacturing steps can proceed without additional plating operations, thus simplifying the overall process while ensuring adequate bonding strength is established beforehand.
2Reliability
If multiple plating steps are performed to form different plating layers on the lead frame, then the adhesion to bonding wires is improved, but the manufacturing time increases
Solution Approach 1:
The patent combines multiple plating operations into a single integrated plating step, forming both the first plating layer and second plating layer in one process. This merging maintains the adhesion properties that would result from multiple separate plating steps while significantly reducing the total manufacturing time by eliminating intermediate steps and handling operations.
Solution Approach 2:
The patent ensures continuous plating action by forming the multi-layer plating structure without interrupting the plating process. This continuous approach maintains the quality and adhesion characteristics of multiple plating layers while minimizing idle time between operations, thereby reducing overall manufacturing time while preserving reliability.
3Manufacturing precision
If a plating layer is formed on the reverse surface of the lead frame, then burr formation during cutting is reduced, but the number of plating steps increases
Solution Approach 1:
The patent incorporates the plating of the reverse surface into the same plating step as the plating of other lead frame surfaces. By forming the first plating layer and second plating layer simultaneously across all surfaces including the reverse surface, the patent reduces burr formation during cutting while avoiding the need for separate plating operations, thus maintaining manufacturing precision without increasing the number of plating steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration simplifies the manufacturing process while maintaining strong bonding strength to circuit boards and enabling easy visual inspection of bonding states.
Implementation Method 1
a first plating layer formed in contact with the first obverse surface and the first reverse surface
Implementation Method 2
the second plating layer is formed in contact with the first recess and the first portion
Data Source
AI summary
A semiconductor device includes a first lead, a semiconductor element, a sealing resin, a first plating layer, and a second plating layer. The first lead has a first obverse surface and a first reverse surface facing opposite from each other in a thickness direction and a first recess recessed from the first reverse surface toward the first obverse surface. The semiconductor element is mounted on the first obverse surface. The sealing resin covers the semiconductor element. The first plating layer is formed in contact with the first obverse surface and the first reverse surface. The first recess is exposed from the sealing resin. The first plating layer includes a first portion covering the first reverse surface. The second plating layer is formed in contact with the first recess and the first portion.