Lead Frame Silver Plating Thickness Control for Chip Protection

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Solution Overview

Problem

In semiconductor device manufacturing, the reduced size and pitch of QFN type semiconductor devices lead to deteriorated mask alignment accuracy during silver plating, resulting in silver plating film on suspending leads that can cause cracking and chipping of semiconductor chips during die bonding due to uncrushed projecting portions.

Innovation Solution

A lead frame manufacturing method where the thickness of the silver plating film on suspending leads is made smaller than on regular leads, and the silver plating on suspending leads is crushed during offset work to prevent projection and ensure proper chip mounting, thereby preventing contact with the semiconductor chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the semiconductor device size and pitch are reduced, then the device becomes more compact and integrated, but the mask alignment accuracy deteriorates causing silver plating to be applied onto suspending leads

Engineering Contradiction:
Improvedevice sizeVSAvoidmask alignment accuracy
Core Design Contradiction:
Volume of moving objectVSManufacturing precision

Solution Approach 1:

The patent applies different plating conditions to different regions of the lead frame. Specifically, the suspending leads are positioned in a region where silver plating is intentionally suppressed or reduced, while the regular leads receive full silver plating. This spatial differentiation of plating quality resolves the contradiction by allowing compact device design without the harmful effect of silver plating on suspending leads

Inventive Principle:
Principle #3Local quality

2Reliability

If silver plating is applied onto suspending leads to ensure proper wire connection, then the electrical connection is improved, but the projecting portions of silver plating cause cracking and chipping of semiconductor chips during die bonding

Engineering Contradiction:
Improvewire connection reliabilityVSAvoidchip cracking and chipping
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent creates a localized plating-free or reduced-plating zone at the tab-side end of suspending leads. This ensures that the silver plating is present on regular leads for reliable wire connection while being absent or minimized on suspending leads near the tab, eliminating the harmful projecting portions that cause chip damage during bonding

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements offset work (bending) of suspending leads before the die bonding process. This preliminary action positions the suspending leads and their silver plating away from the chip mounting area, preventing contact between the chip and any projecting silver plating portions during subsequent bonding operations

Inventive Principle:
Principle #10Preliminary action

3Shape

If offset work is performed on suspending leads with thick silver plating, then the tab height is increased for proper sealing, but the thick silver plating remains uncrushed and projects outward causing chip damage

Engineering Contradiction:
Improvetab heightVSAvoidsilver plating crush completeness
Core Design Contradiction:
ShapeVSManufacturing precision

Solution Approach 1:

The patent ensures that the silver plating on suspending leads is either thinner or selectively applied only in regions that will be crushed during offset work. This localized plating strategy allows the offset work to completely crush the plating, forming a flat surface that prevents chip damage while still achieving the necessary tab height through the bending action

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method prevents cracking and chipping of semiconductor chips during die bonding, enhancing the reliability and quality of the semiconductor device by ensuring the silver plating does not interfere with chip placement.

Implementation Method 1

the silver plating on suspending leads is crushed during offset work

Methodology Applied
Scientific EffectPlastic deformation: Plasticity

Implementation Method 2

The silver plating for the leads of the lead frame is performed through a mask

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS8102035B2Method of manufacturing a semiconductor device
Publication Date: 2012.01.24 RENESAS ELECTRONICS CORP
  • US8102035B2 patent drawing
  • US8102035B2 patent drawing
  • US8102035B2 patent drawing

AI summary

According to the method of manufacturing a semiconductor device, a lead frame is provided wherein the thickness of a tab-side end portion of a silver plating for wire connection formed on each suspending lead 1e is smaller than that of a silver plating formed on each lead. Thereafter, a semiconductor chip is mounted onto a tab. In this case, since the entire surface of the silver plating on the suspending lead 1e is in a crushed state, it is possible to prevent contact of the semiconductor chip with the silver plating when mounting the chip onto the tab. Consequently, in a die bonding process, the semiconductor chip can slide on the tab without contacting the silver plating and thereby making it possible to diminish damage to the semiconductor chip when mounted onto the tab and hence to possibly prevent cracking or chipping of the chip when assembling the semiconductor device.