Lead Frame Recess and Relay Board Layout for Shorter Bond Wires

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Solution Overview

Problem

Conventional semiconductor devices experience short circuits due to bonding wires moving during resin encapsulation, which is exacerbated by long wire lengths.

Innovation Solution

A semiconductor device design featuring a lead frame with a recessed relay board and short bonding wires, where the distance between the lead frame and relay board surfaces is minimized to restrict wire movement, and additional semiconductor chips are connected via shorter conductive paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional lead frames are used with long bonding wires, then connection flexibility is improved, but short circuit risk increases due to wire movement during encapsulation

Engineering Contradiction:

Improveconnection flexibilityVSAvoidshort circuit risk

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces a relay board as an intermediate component that segments the bonding path into two parts: lead frame to relay board, and relay board to semiconductor chip. This segmentation allows each segment to use shorter wires, reducing movement and short circuit risk while maintaining overall connection flexibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The relay board acts as an intermediary component between the lead frame and semiconductor chip. It provides a stable mounting platform that reduces wire length and movement, thereby lowering short circuit risk during encapsulation while preserving connection adaptability.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If bonding wire length is increased to accommodate layout requirements, then ease of manufacturing is improved, but wire movement during encapsulation increases causing short circuits

Engineering Contradiction:

Improvelayout accommodationVSAvoidwire movement control

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent utilizes the vertical dimension by introducing a relay board at a different height level between the lead frame and semiconductor chip. This dimensional change allows for shorter wire runs in the horizontal plane while accommodating layout requirements through vertical stacking.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If relay board is positioned far from lead frame, then mounting flexibility is improved, but distance increases causing longer wires and potential short circuits

Engineering Contradiction:

Improvemounting flexibilityVSAvoidbonding wire length

Core Design Contradiction:

Adaptability or versatilityVSLength of moving object

Solution Approach 1:

The relay board is nested within the recess of the lead frame structure, creating a compact integrated assembly. This nesting arrangement minimizes the distance between components, reducing bonding wire length and movement while maintaining mounting flexibility.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS11810840B2Semiconductor device

Publication Date: 2023.11.07 SHINKO ELECTRIC IND CO LTD

AI summary

A semiconductor device includes a lead frame having a first principal surface which includes a recess, and a second principal surface opposite to the first principal surface, a relay board, disposed in the recess, and having a third principal surface, and a fourth principal surface opposite to the third principal surface, wherein the fourth principal surface opposes a bottom surface of the recess, a first semiconductor chip disposed on the third principal surface, a first conductive material connecting the lead frame and the relay board, and a second conductive material connecting the relay board and the first semiconductor chip. A distance between the second principal surface and the third principal surface is less than or equal to a distance between the second principal surface and the first principal surface.