Semiconductor Lead Frame Segmented Bonding for Stress Relief

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Solution Overview

Problem

Conventional semiconductor packages, such as QFN and CoL, suffer from high tensile and thermal stresses due to large bonding interfaces, leading to die cracking and warpage, which negatively affect the temperature coefficient of offset and capability index, and can result in device failure.

Innovation Solution

A semiconductor package with a lead frame featuring elongated frame members and chip-on lead pads, where the die is attached to minimal portions of the lead frame, reducing the bonding interface surface area and incorporating a flexible structure to minimize stresses, and using a mold compound for encapsulation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If the entire surface of the die flag is coated with adhesive material to bond the entire inactive surface of the die, then the bonding interface surface area is large providing strong adhesion, but high tensile stress is imposed on the die during bonding which can result in die cracking

Engineering Contradiction:

Improvebonding strengthVSAvoidtensile stress on die

Core Design Contradiction:

StrengthVSObject-affected harmful factors

Solution Approach 1:

The patent segments the bonding interface by providing discrete chip-on lead pads instead of a continuous adhesive layer covering the entire die flag surface. This segmentation reduces the total bonding interface area and distributes the bonding stress to specific locations, thereby reducing the tensile stress imposed on the die during bonding while maintaining adequate bonding strength through the concentrated adhesive material on the lead pads.

Inventive Principle:

Principle #1Segmentation

2Stability of the object's composition

If the die flag has a rigid structure to provide mechanical support, then structural stability is improved, but residual thermal stresses are developed at the bonding interface due to CTE mismatch which can warp the package

Engineering Contradiction:

Improvestructural stabilityVSAvoidresidual thermal stress

Core Design Contradiction:

Stability of the object's compositionVSObject-generated harmful factors

Solution Approach 1:

The patent incorporates a stress relief layer between the die flag and the die that acts as a flexible element to accommodate thermal expansion differences. This layer is positioned at the bonding interface where CTE mismatch occurs, allowing it to deform and relieve residual thermal stresses while the overall rigid structure of the die flag maintains structural stability. The flexible stress relief layer prevents warpage by compensating for differential thermal expansion.

Inventive Principle:

Principle #30Flexible shells and thin films

3Ease of manufacture

If adhesive material is dispensed onto the exposed surface of the die flag for bonding, then the bonding process is simple and efficient, but the large bonding interface area combined with rigid lead frame creates high thermal stress

Engineering Contradiction:

Improvebonding process simplicityVSAvoidthermal stress at bonding interface

Core Design Contradiction:

Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent segments the bonding interface into discrete chip-on lead pads rather than using a continuous adhesive layer. This segmentation maintains ease of manufacture by allowing standard adhesive dispensing processes to be used, while the reduced and distributed bonding interface area significantly reduces thermal stress at the bonding interface. The segmented approach preserves manufacturing simplicity while eliminating the harmful thermal stress effect.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution significantly reduces tensile and thermal stresses, preventing die cracking and warpage, enhancing the stability and performance of the semiconductor package by maintaining a low 2nd order Tco and high capability index, even at varying temperatures.

Implementation Method 1

an adhesive material typically is dispensed onto the exposed surface of the die flag, the die is then placed thereon

Methodology Applied

Scientific EffectAdhesion: Adhesive

Implementation Method 2

All of the components are then encapsulated by a mold compound to form the final QFN semiconductor package

Methodology Applied

Scientific EffectPhysical containment: Physical Containment

Implementation Method 3

the rigid nature of the lead frame (particularly the die flag)

Methodology Applied

Scientific EffectRigidity:

Data Source

PatentUS20140264793A1Lead frame for semiconductor package with enhanced stress relief

Publication Date: 2014.09.18 STMICROELECTRONICS INT NV

AI summary

A semiconductor package includes a lead frame, a semiconductor die, bond wires providing an electrical connection between the die and the lead frame, and a mold compound that encapsulates the lead frame, the die and the bond wires. The lead frame includes spaced apart first and second frame members each having an inner peripheral edge and an opposing outer peripheral edge, spaced apart lead pads disposed between the inner peripheral edges of the first and second frame members, and conductive leads disposed proximate to the outer peripheral edge of each of the first and second frame members. The die is mounted on the lead pads.