Lead Frame Layout for Wire-Bond-Free Semiconductor Packaging

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Solution Overview

Problem

The existing semiconductor devices experience increased inductance due to bonding wires, which affects their performance and efficiency, particularly in high-frequency applications.

Innovation Solution

A semiconductor device design that eliminates bonding wires by using a lead frame with drain, source, and gate frames that are directly connected to the transistor electrodes, with the encapsulation resin exposing parts of the lead frame to reduce inductance and enhance heat dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bonding wires are used to connect transistor electrodes to lead frame, then electrical connection is achieved, but inductance increases

Engineering Contradiction:
Improveelectrical connectionVSAvoidinductance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent removes bonding wires from the structure entirely, extracting the harmful element that causes inductance. The lead frame is designed to directly contact and connect to transistor electrodes without intermediate bonding wires, eliminating the inductance problem while maintaining electrical connection functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the functions of electrical connection and structural support into a single integrated lead frame structure. The lead frame directly contacts the transistor electrodes, combining the connection function that previously required separate bonding wires with the structural framework, thereby eliminating inductance-causing intermediate components.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If lead frame is fully encapsulated by resin, then protection is achieved, but heat dissipation is reduced

Engineering Contradiction:
ImproveprotectionVSAvoidheat dissipation
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The patent applies local quality by selectively exposing specific portions of the lead frame (the connection regions contacting transistor electrodes) while encapsulating other portions with resin. This localized approach provides protection where needed while maintaining heat dissipation pathways at critical connection points, balancing protection and thermal management.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If bonding wires are used, then flexibility in connection is achieved, but device complexity increases

Engineering Contradiction:
Improveconnection flexibilityVSAvoidstructure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges multiple functions into the lead frame structure itself, which simultaneously provides mechanical support, electrical connection, and thermal management. By eliminating bonding wires and integrating their connection function directly into the lead frame, the overall device complexity is reduced while maintaining connection adaptability through the lead frame's design.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11901316B2Semiconductor device
Publication Date: 2024.02.13 ROHM CO LTD
  • US11901316B2 patent drawing
  • US11901316B2 patent drawing
  • US11901316B2 patent drawing

AI summary

A semiconductor device includes a lead frame, a transistor, and an encapsulation resin. The lead frame includes a drain frame, a source frame, and a gate frame. The drain frame includes drain frame fingers. The source frame includes source frame fingers. The drain frame fingers and the source frame fingers are alternately arranged in a first direction and include overlapping portions as viewed from a first direction. In a region where each drain frame finger overlaps the source frame fingers as viewed in the first direction, at least either one of the drain frame fingers and the source frame fingers are not exposed from the back surface of the encapsulation resin.