Lead Frame Layout for Symmetric Power Semiconductor Switching

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Solution Overview

Problem

Conventional molded power semiconductor package designs for high-power applications suffer from asymmetrical gate contact connections between high-side and low-side switching nodes, leading to different switching speeds and potential oscillations that can damage the modules.

Innovation Solution

The proposed molded power semiconductor package design includes a symmetrical connection frame with structured metal frames overlying the power semiconductor dies, reducing stray inductance and ensuring even switching speeds for both high-side and low-side switches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional molded power semiconductor package designs are used, then the package structure is simple, but the gate contacts are asymmetrical leading to different switching speeds and potential oscillations

Engineering Contradiction:

Improveswitching speed symmetryVSAvoidpackage structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies asymmetry principle by intentionally designing symmetrical gate contact connections for both high-side and low-side switches, which is unconventional. The connection frame is configured such that gate contacts to high-side switches and low-side switches have equal length and equivalent inductance, creating a balanced symmetrical structure that eliminates switching speed differences and oscillations.

Inventive Principle:

Principle #4Asymmetry

2Device complexity

If asymmetrical gate contact connections are used, then the package structure is simpler, but oscillations occur due to different switching speeds

Engineering Contradiction:

Improveconnection frame structureVSAvoidoscillations

Core Design Contradiction:

Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent implements equipotentiality by ensuring that gate contacts for high-side and low-side switches have equal electrical characteristics. The connection frame is designed so that gate contact inductances are matched, creating equivalent electrical potential conditions for both switching nodes, thereby preventing oscillations caused by asymmetrical switching speeds.

Inventive Principle:

Principle #12Equipotentiality

3Reliability

If derating is applied to prevent oscillations, then module reliability improves, but power output is reduced

Engineering Contradiction:

Improvemodule stabilityVSAvoidpower output

Core Design Contradiction:

ReliabilityVSPower

Solution Approach 1:

The patent converts the harmful effect of asymmetrical gate contacts into a benefit by designing a symmetrical connection frame structure. Instead of derating to prevent oscillations, the invention eliminates the root cause of oscillations through symmetrical design, allowing the module to operate at full power without stability issues. The symmetrical structure transforms the potential harm of asymmetry into the benefit of balanced performance.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS12211824B2Power semiconductor package having first and second lead frames

Publication Date: 2025.01.28 INFINEON TECHNOLOGIES AG

AI summary

A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.