Lead Frame Bonding Layout for Void-Safe MOSFET Heat Dissipation
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Solution Overview
Problem
Void content in solder joints of semiconductor devices reduces heat dissipation and creates a thermal runaway weak structure, limiting the safe operation area and reliability of semiconductor devices, particularly in vertical MOSFETs.
Innovation Solution
The semiconductor device employs a lead frame configuration with a first bonding material having a thinner film thickness below the control electrode and a thicker film thickness on the bed, minimizing void formation and enhancing thermal conductivity by ensuring the voids are more easily released, thus maintaining low thermal resistivity and ensuring a wide safe operation area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder is used to join the source electrode and connector, then electrical connection is achieved, but void content in the solder reduces heat dissipation and creates thermal runaway risk
Solution Approach 1:
The patent changes the physical parameters of the bonding material by using a bonding material with different properties than traditional solder, specifically one that can be controlled to have minimal void formation and optimized thermal conductivity, thereby improving heat dissipation while maintaining electrical connection reliability
Solution Approach 2:
The patent applies different film thicknesses of bonding material in different locations: a first film thickness below the control electrode and a second film thickness on the bed, optimizing thermal and electrical properties locally to prevent void formation in critical areas while ensuring adequate bonding elsewhere
2Reliability
If uniform film thickness of bonding material is used, then manufacturing simplicity is maintained, but void formation cannot be prevented in critical areas
Solution Approach 1:
The patent implements local quality by specifying different film thicknesses for different locations: a first film thickness of the bonding material below the control electrode and a second film thickness on the bed, allowing optimization of thermal and electrical properties in critical areas while maintaining manufacturing feasibility
Solution Approach 2:
The patent applies preliminary action by pre-configuring the bonding material film thickness distribution before assembly, ensuring that the first film thickness below the control electrode is controlled to prevent void formation, thereby eliminating the need for post-assembly void removal processes
3Reliability
If thicker bonding material is used, then void formation is reduced, but thermal conductivity may be compromised
Solution Approach 1:
The patent applies local quality by using different film thicknesses in different locations: a first film thickness below the control electrode optimized for void prevention, and a second film thickness on the bed optimized for thermal conduction, thereby simultaneously achieving low void content and low thermal resistivity
Solution Approach 2:
The patent changes the film thickness parameter of the bonding material to optimize both void prevention and thermal conductivity, specifically controlling the first film thickness below the control electrode to a range that prevents void formation while maintaining adequate thermal contact
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces thermal resistivity, ensures high reliability, and expands the safe operation area of semiconductor devices by preventing voids from forming below the control electrode, facilitating efficient heat dissipation and maintaining current magnitude.
Implementation Method 1
a first bonding material provided between the first upper surface and the semiconductor chip, the first bonding material joining the first upper surface and the semiconductor chip
Implementation Method 2
a first film thickness of the first bonding material portion below the control electrode being thinner than a second film thickness of the second bonding material portion on the second portion of the first bed
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3
AI summary
A semiconductor of an embodiment includes a lead frame including a first bed; a first post; a second post; a semiconductor chip provided on the first upper surface, the semiconductor chip; a first bonding material provided between the first upper surface and the semiconductor chip, the first bonding material joining the first upper surface and the semiconductor chip, a first film thickness of the first bonding material portion being thinner than a second film thickness of the second bonding material portion; a first connector; a second bonding material; and a third bonding material.