Lead Frame Carrier Fabrication for Wafer Level Package

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Solution Overview

Problem

Existing semiconductor package substrates fabricated using PCB substrates face issues with sawing burr and inadequate heat dissipation characteristics, making them unsuitable for structures requiring efficient heat transfer and physical strength.

Innovation Solution

A method of fabricating a carrier structure using a lead frame in a wafer level package, involving first and second half etching processes with a dry film resist barrier to reduce sawing burr and enhance heat dissipation, where the etching rates are differentiated to minimize burr formation and improve thermal conductivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a PCB substrate with CCL is used to fabricate a carrier structure, then the manufacturing process is simple and no sawing burr problem occurs, but the heat dissipation characteristics are insufficient

Engineering Contradiction:

Improveease of manufactureVSAvoidheat dissipation characteristics

Core Design Contradiction:

Ease of manufactureVSTemperature

Solution Approach 1:

The patent changes the material parameter from CCL (copper clad laminate) to lead frame material, which has superior thermal conductivity. This parameter change resolves the contradiction by providing excellent heat dissipation characteristics while maintaining manufacturability through the modified etching process

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent uses a composite structure combining lead frame material with resin filling in trenches, creating a carrier structure that leverages the thermal conductivity of metal while providing structural stability and electrical insulation where needed

Inventive Principle:

Principle #40Composite materials

2Temperature

If a lead frame is used to fabricate a carrier structure, then the heat dissipation characteristics and strength are improved, but sawing burr is generated during the etching process

Engineering Contradiction:

Improveheat dissipation characteristicsVSAvoidsawing burr

Core Design Contradiction:

TemperatureVSManufacturing precision

Solution Approach 1:

The etching process is segmented into two distinct stages: first half etching that stops before completing the trench, and second half etching that completes the trench after resin filling. This segmentation allows control over burr formation at each stage, resolving the manufacturing precision issue while maintaining the thermal benefits of lead frame

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The resin filling is performed as a preliminary action before completing the etching process. By filling the trench with resin before the second half etching, the process prevents burr formation on the flexible circuit substrate while still achieving the desired lead frame structure for heat dissipation

Inventive Principle:

Principle #10Preliminary action

3Ease of manufacture

If uniform etching rate is applied across the entire base substrate, then the manufacturing process is simple, but sawing burr cannot be effectively reduced

Engineering Contradiction:

Improveetching process simplicityVSAvoidsawing burr reduction

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies different etching rates to different regions of the base substrate: a first etching rate in areas where memory chips are attached, and a second etching rate in areas where chips are not attached. This local differentiation reduces sawing burr while managing the complexity of the etching process through region-specific control

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method achieves reduced sawing burr and enhanced heat dissipation characteristics, providing a carrier package with high strength and improved thermal conductivity, suitable for protecting chips from physical impact and efficient heat discharge.

Implementation Method 1

forming a trench and a post by performing first half etching on an upper surface of a base substrate comprising a conductive material

Methodology Applied

Scientific EffectEtching:

Implementation Method 2

filling the first-half-etched surface with resin of an insulating material

Methodology Applied

Scientific EffectFilling:

Implementation Method 3

a method of fabricating a carrier structure having excellent heat dissipation characteristics and high strength by using a lead frame

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS11227775B2Method of fabricating carrier for wafer level package by using lead frame

Publication Date: 2022.01.18 HAESUNG CO LTD

AI summary

According to an embodiment of the disclosure, a method of fabricating a carrier for a wafer level package (WLP) by using a lead frame, wherein the lead frame is fabricated by forming a trench and a post by performing first half etching on an upper surface of a base substrate comprising a conductive material, filling the first-half-etched surface with resin of an insulating material, removing the resin exposed to outside of the trench so that an upper surface of the trench and an upper surface of the resin are at a same level, and performing second half etching on a lower surface of the base substrate, in which a memory chip is attached to the lower surface of the base substrate.