Lead Mount Layout for Thermal-Stress-Resistant Semiconductor Packages
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Solution Overview
Problem
Conventional semiconductor devices experience stress-induced cracking or peeling of solder bonds due to thermal expansion, which compromises the mounting strength.
Innovation Solution
The semiconductor device is designed with outer reverse-surface mount portions having a larger area than inner portions, positioned at the outermost edges, to distribute thermal stress evenly and prevent cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform mount portions are used across all leads, then manufacturing is simple, but thermal stress concentrates at outer edges causing solder cracking
Solution Approach 1:
The patent applies local quality by making the mount portions asymmetric: outer reverse-surface mount portions have a larger area than inner reverse-surface mount portions. This local variation in geometry allows the outer portions to bear more thermal stress during temperature changes, preventing solder cracking at critical locations while maintaining overall manufacturing simplicity through a systematic design pattern.
2Device complexity
If all mount portions have equal area, then structure is simple, but stress distribution is uneven leading to solder failure
Solution Approach 1:
The patent implements asymmetry by designing outer reverse-surface mount portions with a larger area compared to inner reverse-surface mount portions. This asymmetric configuration optimizes stress distribution during thermal cycling, with larger outer portions accommodating higher stress concentrations at the edges. The asymmetric design maintains reasonable structural simplicity while significantly improving solder bond strength and preventing cracking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the mounting strength by significantly reducing solder cracking under thermal stress, ensuring reliable bonding and durability.
Implementation Method 1
a sealing resin covering the semiconductor element and a part of each of the leads
Implementation Method 2
The mount portions are bonded to a circuit board with solder, for example
Implementation Method 3
In accordance with the specifications of the semiconductor device or the use environment, stress may be generated in the solder for bonding the mount portions and the circuit board
Data Source
AI summary
A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin covering the semiconductor element and a part of each lead. The sealing resin includes a first edge, a second edge perpendicular to the first edge, and a center line parallel to the first edge. The reverse surfaces of the respective leads include parts exposed from the sealing resin, and the exposed parts include an outer reverse-surface mount portion and an inner reverse-surface mount portion that are disposed along the second edge of the sealing resin. The inner reverse-surface mount portion is closer to the center line of the sealing resin than is the outer reverse-surface mount portion. The outer reverse-surface mount portion is greater in area than the inner reverse-surface mount portion.