Lead-On-Chip Interconnect Structure for High-Current Semiconductor Packaging
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Solution Overview
Problem
Semiconductor device packaging faces challenges in accommodating sophisticated features and applications while maintaining reliability, performance, and minimizing costs, as existing configurations often result in lower reliability and higher costs.
Innovation Solution
The semiconductor device employs lead-on-chip interconnects with a leadframe partially encapsulated in an encapsulant, where one end of the leads is affixed to bond pads and the other end is exposed, allowing for higher current operation and flexible interconnection through a package substrate, which can be formed as a build-up or pre-formed substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional bond wires are used for interconnection, then device complexity is reduced, but current handling capability and reliability deteriorate
Solution Approach 1:
The patent merges the leadframe structure with the semiconductor die by directly affixing lead ends to bond pads, eliminating the need for separate bond wires. This integration combines the interconnection function into the existing leadframe, improving reliability while avoiding additional complexity from wire bonding processes
Solution Approach 2:
The leadframe leads serve multiple functions: they provide structural support, electrical interconnection, and current carrying capability. By making the leads multi-functional, the patent eliminates the need for dedicated bond wires, thereby improving reliability without increasing overall device complexity
2Power
If bond wires are used for interconnection, then manufacturing process is simpler, but current handling capability deteriorates
Solution Approach 1:
The patent combines the interconnection and current carrying functions into the leadframe structure itself. The leads are directly affixed to bond pads, creating a robust electrical path that can handle high currents without requiring separate wire bonding steps, thus maintaining manufacturing simplicity while improving power capability
3Adaptability or versatility
If sophisticated features are added to semiconductor devices, then functionality is improved, but package reliability and performance deteriorate
Solution Approach 1:
The leadframe leads are designed to perform multiple functions including mechanical support, electrical interconnection, and high-current carrying. This multi-functionality allows the package to accommodate sophisticated device features while maintaining robust reliability through the strengthened interconnection structure
4Reliability
If traditional packaging configurations are used, then manufacturing cost is reduced, but performance and reliability deteriorate
Solution Approach 1:
The patent merges the interconnection function into the leadframe structure, eliminating the need for separate wire bonding materials and processes. This integration reduces material costs and simplifies manufacturing while simultaneously improving reliability through the more robust direct-attach interconnection structure
Data Source
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AI summary
A method of forming a semiconductor device is provided. The method includes placing a semiconductor die and a leadframe on a carrier substrate. The semiconductor die includes a plurality of bond pads and the leadframe includes a plurality of leads. A first lead of the plurality of leads has a proximal end affixed to a first bond pad of the plurality of bond pads and a distal end placed on the carrier substrate. At least a portion of the semiconductor die and the leadframe is encapsulated with an encapsulant. The carrier substrate is separated from a first major side of the encapsulated semiconductor die and leadframe exposing a distal end portion of the first lead. A package substrate is applied on the first major side.