Semiconductor Lead Pin Groove Design for Reflow Stability

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Solution Overview

Problem

The use of lead-free solders in semiconductor packaging leads to issues where the semiconductor loading lead pins tilt during reflow, causing defects as the solder connecting them melts, resulting in voids that can tilt the pins and prevent proper attachment of IC chips to daughter boards.

Innovation Solution

A semiconductor loading lead pin design featuring a flange with a flat portion and multiple groove portions that extend from the side end towards the center, allowing voids to escape sideways during reflow, maintaining perpendicularity and preventing pin tilting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If lead-free solder with higher melting point is used for IC chip connection, then environmental compatibility is improved, but the solder for semiconductor loading lead pin melts during reflow causing pin tilting

Engineering Contradiction:
Improveenvironmental compatibilityVSAvoidpin positioning accuracy
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The flange is segmented into multiple groove portions that divide the solder joint into separate regions. This segmentation allows voids to escape through specific pathways during reflow, preventing the solder from pushing the flange upward and causing pin tilting, while still using lead-free solder for environmental compatibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The groove portions act as intermediary channels that facilitate void escape during the reflow process. These grooves provide a controlled pathway for gas evacuation, mediating between the melting solder and the flange structure to prevent harmful upward pressure that would cause pin tilting.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Extent of automation

If reflow process is used to melt solder bumps for IC chip connection, then automated assembly is improved, but void expansion pushes flange upward causing pin tilting

Engineering Contradiction:
Improveautomated assemblyVSAvoidpin perpendicularity
Core Design Contradiction:
Extent of automationVSManufacturing precision

Solution Approach 1:

The groove portions extract or remove voids from the solder joint during reflow by providing escape pathways. This extraction prevents void accumulation and expansion that would otherwise push the flange upward and compromise pin perpendicularity during automated reflow assembly.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The groove portions are pre-formed in the flange structure before reflow, creating predetermined void escape pathways. This preliminary structural preparation ensures that when reflow occurs, voids have ready-made channels to escape through, maintaining pin perpendicularity during automated assembly.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If solder melting point is differentiated for T pin and IC chip connection, then selective soldering is improved, but lead-free solder causes both solders to melt at same temperature

Engineering Contradiction:
Improveselective solderingVSAvoidsolder melting point
Core Design Contradiction:
Adaptability or versatilityVSTemperature

Solution Approach 1:

The flange structure incorporates local quality variations through groove portions at specific locations. This local structural modification creates different functional zones: areas with grooves allow void escape, while other areas maintain solid solder joints, enabling selective behavior in the solder connection during reflow with lead-free solder.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively prevents pin tilting and ensures secure attachment by allowing voids to escape along the groove portions, maintaining the lead pin's perpendicularity and preventing defects during the reflow process.

Implementation Method 1

when reflow is carried out to load the IC chip 50 the solder 48 for connection is melted as shown in FIG. 3(D) and at the same time, the void B in the solder is expanded so that the flange 20 is pushed up by that void thereby tilting the semiconductor loading lead pin 10

Methodology Applied
Scientific EffectVoid expansion and escape:

Data Source

PatentUS7723620B2Lead pin for mounting semiconductor and printed wiring board
Publication Date: 2010.05.25 IBIDEN CO LTD
  • US7723620B2 patent drawing
  • US7723620B2 patent drawing
  • US7723620B2 patent drawing

AI summary

A semiconductor loading lead pin that does not tilt at a time of reflow. A void is sometimes left in solder between an electrode pad and the flange of a semiconductor loading lead pin. When reflow is carried out to load an IC chip, the solder for connection is melted and at the same time, the void in the solder is expanded. The solder escapes sideway along the groove portion, and thereby a flange is not raised by the void so that the semiconductor loading lead pin is not tilted.