Lead Spacing Layout for Semiconductor Package Insulation Reliability

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Solution Overview

Problem

Semiconductor devices face dielectric breakdown due to large potential differences between elements within a single package, leading to malfunctions and reduced reliability.

Innovation Solution

The semiconductor device design includes a conductive support with leads spaced apart by a distance determined by a formula that considers insulation life, resin material constants, and voltage, ensuring insulated signal transmission between semiconductor elements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple elements with different power voltages are disposed in a single package, then device integration is improved, but dielectric breakdown risk increases

Engineering Contradiction:
Improvedevice integrationVSAvoiddielectric breakdown risk
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies local quality by spacing leads differently based on their voltage levels. High-voltage leads are spaced farther apart than low-voltage leads, creating localized insulation characteristics matched to the voltage requirements of each lead pair. This resolves the contradiction by enabling high device integration while maintaining reliability through voltage-appropriate spacing.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the physical parameter of lead spacing distance based on voltage levels. By establishing that distance d1 between leads carrying different power voltages must exceed a calculated threshold d0 (based on insulation life requirements, resin material properties, and voltage magnitude), the patent dynamically adjusts spacing parameters to prevent dielectric breakdown while maximizing integration.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If distance between leads is increased to prevent dielectric breakdown, then reliability is improved, but device area increases

Engineering Contradiction:
Improvedielectric breakdown suppressionVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent implements local quality by applying different spacing requirements to different lead pairs based on their voltage characteristics. Only leads carrying different power voltages require increased spacing, while leads at the same voltage level can be closely spaced. This selective approach suppresses dielectric breakdown risk without unnecessarily increasing overall device area.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent applies partial action by enforcing increased spacing only where necessary (between leads with different power voltages) rather than uniformly across all leads. The spacing requirement is precisely targeted to the specific condition that causes dielectric breakdown, avoiding excessive area consumption while maintaining reliability.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250300119A1Semiconductor device, method for designing the same, and method for manufacturing the same
Publication Date: 2025.09.25 ROHM CO LTD
  • US20250300119A1 patent drawing
  • US20250300119A1 patent drawing
  • US20250300119A1 patent drawing

AI summary

A semiconductor device is provided with a first lead and a second lead spaced apart from each other in a first direction, a first semiconductor element including a first functional part and supported by the first lead, and a second semiconductor element including a second functional part and supported by the second lead. Each of the first functional part and the second functional part transmits an electrical signal in an insulated state. The distance d1 between the first lead and the second lead in the first direction is greater than a predetermined distance d0.