Lead Surface Plating for Stronger Semiconductor Solder Joints
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Solution Overview
Problem
Conventional semiconductor devices experience issues with solder cracking or detachment due to stress, leading to reduced mounting strength on circuit boards.
Innovation Solution
A semiconductor device design featuring leads with exposed portions covered by a surface plating layer formed through substitutional electroless plating, enhancing solder wettability and mounting strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional leads without surface plating are used, then manufacturing simplicity is maintained, but solder bonding strength deteriorates due to stress-induced cracking
Solution Approach 1:
The patent applies surface plating layers selectively to specific regions of the leads (exposed portions) rather than the entire lead structure. This localized treatment enhances solder bonding strength at critical bonding interfaces while avoiding unnecessary complexity in non-critical areas, thus resolving the contradiction between bonding strength and structural simplicity.
Solution Approach 2:
The patent employs composite material structures by combining base lead materials with surface plating layers (such as solder plating or protective plating). This composite approach improves solder bonding strength through the synergistic properties of different materials while maintaining overall structural simplicity through integrated manufacturing processes.
2Reliability
If surface plating layers are added to leads, then solder wettability and bonding strength improve, but manufacturing process complexity increases
Solution Approach 1:
The surface plating layers are formed on the leads during the manufacturing process before the semiconductor device is assembled and mounted. This preliminary application of plating ensures that the leads are pre-prepared with optimal solder wettability and bonding characteristics, improving mounting reliability while avoiding the need for additional post-assembly processing steps.
Solution Approach 2:
The manufacturing process is designed to automatically apply surface plating layers to the exposed portions of leads through integrated plating operations. This self-service approach within the manufacturing flow improves reliability without requiring separate manual intervention or complex multi-stage processes, thus maintaining ease of manufacture.
3Area of stationary object
If leads are made longer to provide more exposed portions for bonding, then bonding area increases, but device height increases
Solution Approach 1:
Instead of uniformly increasing lead length throughout, the patent applies surface plating layers to specific exposed portions of the leads that are optimally positioned for bonding. This localized enhancement of bonding surfaces increases effective bonding area without requiring proportional increases in overall lead length, thus avoiding excessive device height.
Solution Approach 2:
The patent enhances bonding area by utilizing the surface dimension through plating layer coverage rather than increasing bonding area through lead length extension in the vertical dimension. This dimensional shift allows for increased bonding area while maintaining compact device height by optimizing surface utilization rather than volumetric expansion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The surface plating layers improve the bonding strength of the semiconductor device to circuit boards, reducing manufacturing costs and maintaining a compact design without protrusions.
Implementation Method 1
By substitutional electroless plating, a surface plating layer is formed at least on a part of exposed portions of the lead frame that are exposed from the sealing resin.
Data Source
AI summary
A semiconductor device includes a predetermined number of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin that covers the semiconductor element and a part of each lead. Each lead includes some portions exposed from the sealing resin. A surface plating layer is formed on at least one of the exposed portions of the respective leads.