Leaded Component Vertical Interconnection in SiP
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Solution Overview
Problem
Existing microelectronic packaging methods face challenges in integrating microelectronic components with large footprints into System-in-Packages (SiPs) without significantly increasing the overall planform dimensions, often requiring complex and costly backside interconnection structures like Redistribution Layers (RDLs) and Through Package Vias (TPVs).
Innovation Solution
The integration of microelectronic components with large footprints is achieved by positioning them adjacent to the backside of a core package in a stacked relationship, using elongated leads that route through or around the core package, and establishing electrical connections with reflowed solder or other conductive materials, eliminating the need for backside RDLs and TPVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large footprint component is embedded within the molded body, then the component can be integrated into the SiP, but the overall planform dimensions of the SiP increase significantly
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked arrangement by positioning the large footprint component vertically above or below the molded body. This vertical stacking enables the component to be integrated without increasing the horizontal planform dimensions, effectively utilizing the Z-dimension to resolve the space conflict.
Solution Approach 2:
The patent implements a nested configuration where the large footprint component is positioned within the vertical envelope of the SiP structure, with its leads extending through or around the molded body. This nesting approach allows the component to occupy vertical space rather than horizontal space, maintaining a compact footprint while accommodating the large component.
2Area of stationary object
If the large footprint component is mounted to the package backside in a stacked arrangement, then the SiP planform dimensions are minimized, but the manufacturing process requires build-up of Redistribution Layers or formation of Through Package Vias which increases cost and complexity
Solution Approach 1:
The patent extracts the complex backside interconnection structures (Redistribution Layers and Through Package Vias) from the manufacturing process by routing the component leads through pre-formed openings or around the periphery of the molded body. This extraction eliminates the need for additional RDL build-up steps and TPV formation, significantly simplifying the manufacturing process while maintaining the compact stacked arrangement.
Solution Approach 2:
Instead of bringing interconnection structures up to the component leads (the conventional approach requiring RDLs and TPVs), the patent inverts the approach by routing the leads through or around the molded body to access existing interconnection structures on the front side or within the body. This inversion eliminates the need for complex backside interconnection build-up.
3Adaptability or versatility
If sufficient area is allocated on the package frontside to accommodate large footprint components, then component integration is enabled, but the presence of Ball Grid Array or other frontside contact arrays reduces available area
Solution Approach 1:
The patent resolves the area conflict by moving the large footprint component from the two-dimensional frontside plane to the three-dimensional vertical space. By stacking the component above or below the molded body, the frontside area remains fully available for BGAs and other contact arrays, while the large component is accommodated in the vertical dimension without spatial conflict.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for compact SiP designs with large footprint components while minimizing manufacturing complexity and cost, enabling efficient production on a molded panel or wafer level, thus maintaining throughput and efficiency.
Implementation Method 1
establishing electrical connections with reflowed solder
Implementation Method 2
electrical connections with reflowed solder
Data Source
AI summary
System-in-Packages (SiPs) and methods for producing SiPs are provided. In one embodiment, the above-described SiP fabrication method includes the step or process of forming a through-hole in a core package, the core package containing an electrically-conducive routing feature exposed at a sidewall surface of the through-hole. A leaded component is positioned adjacent the core package such that an elongated lead of the leaded component extends into the through-hole. An electrically-conductive material, such as solder, is then applied into the through hole to electrically couple the elongated lead of the leaded component to the electrically-conductive routing feature of the core package.