Leaded Package System with Partially Exposed Leads
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Solution Overview
Problem
Current integrated circuit packaging technologies face limitations in increasing circuit density, reducing delamination and adhesive failures, and achieving a lower profile, while also being cost-effective and efficient, especially in multi-chip modules where individual chip testing is challenging.
Innovation Solution
The proposed solution involves a frame-based integrated circuit package system where a leaded package with partially exposed leads is encapsulated, allowing for improved connectivity and reduced adhesive use, enabling more efficient manufacturing and design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-chip modules are assembled before chip testing, then manufacturing efficiency is improved, but reliability deteriorates due to inability to identify defective chips
Solution Approach 1:
The patent applies preliminary action by performing chip assembly into multi-chip modules before final packaging, while maintaining the ability to test individual chips. The leaded package design allows chips to be mounted and connected on a leadframe structure, enabling intermediate testing capabilities before the chip is fully encapsulated in the final package, thus resolving the contradiction between early assembly for efficiency and defect detection for reliability
2Reliability
If chips are individually encapsulated in molded plastic, then protection is improved, but circuit density deteriorates due to large package size
Solution Approach 1:
The patent applies the nested doll principle by placing multiple chips and their individual encapsulants within a single shared package structure. Multiple individually protected chips are nested together on a common leadframe, with a final encapsulant covering all chips. This allows each chip to maintain its protective encapsulation while achieving high circuit density through vertical stacking rather than horizontal spreading
3Strength
If adhesive is used to mount chips, then mechanical support is improved, but reliability deteriorates due to adhesive failures and delamination
Solution Approach 1:
The patent applies the extraction principle by removing adhesive materials from the chip mounting process. Instead of using adhesive to attach chips to the leadframe, the design uses direct mechanical support through the leadframe structure itself and wirebond connections, eliminating the adhesive layer that causes delamination and reliability failures
4Reliability
If wirebonding is used for connectivity, then electrical connection is improved, but device complexity deteriorates due to additional components and steps
Solution Approach 1:
The patent applies merging by integrating the leadframe structure to serve multiple functions simultaneously: it provides mechanical support for the chips, serves as the electrical interconnect structure replacing wirebonds, and acts as the package substrate. This consolidation of support and connectivity functions into a single integrated structure reduces device complexity while maintaining reliable electrical connections
Data Source
AI summary
A method for manufacturing an integrated circuit package system includes: providing a frame; attaching a leaded package having leads adjacent the frame wherein the leads extend towards a side opposite the frame; and applying a package encapsulant over the leaded package having the leads partially exposed opposite the frame.