Selective Bond Pad Plating for Copper Overetch in Lead Frames
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing cost of palladium and the issue of copper overetch during semiconductor device fabrication, leading to device failures and defects, particularly in semiconductor devices with high copper density.
Innovation Solution
A method involving selective plating of nickel and palladium or gold layers only on bond pad conductors, while omitting these layers on conductor traces, reducing palladium usage and preventing copper overetch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If palladium plating is used on all copper surfaces, then bondability and reliability are improved, but production costs increase and copper overetch occurs
Solution Approach 1:
The patent applies different plating treatments to different locations: bond pads receive nickel and palladium plating for optimal bondability, while conductor traces receive only copper plating. This localized differentiation reduces overall palladium consumption while maintaining reliability where it is most needed.
Solution Approach 2:
The patent segments the conductor layer into functionally distinct regions (bond pads and conductor traces) and applies different plating processes to each segment. Bond pads undergo complete nickel-palladium plating, while conductor traces undergo selective copper plating only, eliminating unnecessary palladium usage in non-bonding areas.
2Reliability
If palladium plating is used on all copper surfaces, then bondability is improved, but production costs increase
Solution Approach 1:
The patent implements local quality by applying expensive nickel-palladium plating only to bond pads where bondability is critical, while using inexpensive copper plating for conductor traces. This selective approach significantly reduces material costs while maintaining the necessary bondability for wire bonding operations.
3Reliability
If copper density is increased, then electrical performance is improved, but copper overetch during production increases
Solution Approach 1:
The patent applies local quality by providing nickel-palladium plating protection only on bond pads where copper is present, while conductor traces without palladium plating are protected from overetch through alternative means. This localized protection strategy prevents copper overetch in high-density areas while maintaining electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces palladium usage, lowers production costs, and enhances the reliability of wire bonds by preventing copper overetch, thereby increasing yield and reducing device defects.
Implementation Method 1
The nickel and palladium plating layers prevent copper diffusion and tarnish of the bond pads
Implementation Method 2
The nickel and palladium plating layers prevent copper diffusion and tarnish of the bond pads, and increase bondability of the bond pads for wire bonding
Implementation Method 3
depositing a seed layer over a device side surface of a semiconductor substrate
Implementation Method 4
patterning the first photoresist layer to form bond pad openings corresponding to bond pad positions and forming trace openings corresponding to conductor traces
Implementation Method 5
plating conductor material in the bond pad openings and the trace openings to form bond pad conductors and conductor traces
Implementation Method 6
plating a nickel layer onto the upper surface of the bond pad conductors
Implementation Method 7
plating a palladium or gold layer onto the nickel layer to form bond pads comprising the bond pad conductor, the nickel layer, and the palladium or gold layer
Implementation Method 8
etching the seed layer to remove the seed layer from the semiconductor substrate
Data Source
AI summary
A described example includes: a semiconductor die having a device side surface and an opposing backside surface, the backside surface mounted to a die pad of a lead frame, the lead frame comprising conductive leads spaced from the die pad; a conductor layer overlying the device side surface; bond pads including bond pad conductors formed in the conductor layer, a nickel layer over the bond pad conductors, and a palladium or gold layer over the nickel layer; conductor traces formed in the conductor layer, the conductor traces free from the nickel layer and the palladium or gold layer; bond wires bonded to the bond pads electrically coupling the bond pads to conductive leads; and mold compound covering the semiconductor die, the bond pads, the bond wires, and portions of the lead frame, wherein portions of the conductive leads are exposed from the mold compound to form terminals.