Leadframe Carrier Connecting Pads for High I/O Density
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Solution Overview
Problem
Conventional leadframe semiconductor packages face limitations in providing high I/O density due to costly and complex manufacturing processes, including etching or cutting, which can lead to cracks, moisture invasion, and ineffective soldering, while also causing resin flash issues.
Innovation Solution
A semiconductor package and manufacturing method using a leadframe with a carrier having exposed connecting pads, where the carrier's size is larger than the die pad, allowing bonding wires to connect the chip to both the leadframe and carrier pads, and a package encapsulant is formed to expose the carrier and lead surfaces, preventing resin flash and eliminating the need for separation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If etching or cutting processes are used to create connecting pads on the carrier, then I/O connections can be increased, but cracks and structural weakness occur
Solution Approach 1:
The carrier is divided into multiple isolated connecting pads rather than a continuous structure. Each pad is independently formed through photolithography patterning, allowing electrical isolation and independent functionality while maintaining overall structural integrity of the carrier substrate.
Solution Approach 2:
Multiple connecting pads are created by copying the pad pattern across the carrier surface through photolithography. This replication process generates numerous I/O connections without requiring repeated etching or cutting operations, thereby maintaining structural integrity while increasing connection density.
2Ease of manufacture
If conventional leadframe structure with leads on four sides is used, then manufacturing is simple, but I/O density is limited
Solution Approach 1:
The connecting pads are distributed across the top and bottom surfaces of the carrier in a planar array configuration, transitioning from the conventional one-dimensional perimeter lead arrangement to a two-dimensional surface utilization. This dimensional change enables significantly higher I/O density while maintaining manufacturing simplicity through standard photolithography processes.
3Quantity of substance
If ball grid array substrate with trace patterns is used, then I/O density is high, but manufacturing cost and complexity increase
Solution Approach 1:
The invention extracts and eliminates the complex multi-layer trace pattern system from the BGA substrate. Instead, isolated connecting pads are directly formed on the carrier surface through simple photolithography, removing the need for complex internal routing circuits and vias while maintaining high I/O density.
Solution Approach 2:
Instead of creating continuous trace patterns that require complex routing and via structures, the invention uses discrete isolated pads that directly expose connection points. This inverted approach simplifies the fabrication process by eliminating the need for complex trace layout design and multi-step patterning processes.
4Quantity of substance
If leads are bent and mounted to increase I/O connections, then connection density improves, but resin flash and encapsulation issues occur
Solution Approach 1:
The connecting pads are pre-formed on the carrier surface before the encapsulation process. This preliminary formation ensures proper pad positioning and exposes the pads at the correct height, preventing resin flash from obscuring the connection points and eliminating the need for post-encapsulation lead bending and positioning adjustments.
Data Source
AI summary
A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier s greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.