Leadframe Connection Clip for Low Parasitic Inductance
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Solution Overview
Problem
Parasitic inductances in semiconductor devices cause damage to drivers and power transistors at high switching rates due to high di/dt currents, especially when power return connections are common or separate, leading to voltage-induced damage.
Innovation Solution
A semiconductor device with an integrated power transistor and driver is designed using a leadframe with connection clips that minimize parasitic inductance by directly attaching the source of one transistor to the drain of another and connecting them via a low-resistance, low-inductance clip to a common external node, reducing voltage stress and oscillations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the power return connection for the driver circuit is common with the power return connection of the MOS power transistor, then the device complexity is reduced, but parasitic inductance increases causing voltage damage at high switching rates
Solution Approach 1:
The power return path is segmented into separate regions: a first power return region for the driver circuit and a second power return region for the MOS power transistor. This segmentation allows each circuit to have its own dedicated return path, reducing parasitic inductance while maintaining manageable device complexity through systematic layout organization.
Solution Approach 2:
A common power return node is introduced as an intermediary connection point that receives current from both the driver circuit and the MOS power transistor through separate inductance paths. This mediator structure enables independent return paths while still providing a unified connection to the ground or supply node, resolving the contradiction between simplicity and inductance reduction.
2Productivity
If high switching rates are used to improve productivity, then the output power increases, but parasitic inductance causes high di/dt current resulting in voltage damage
Solution Approach 1:
The separate power return paths and common power return node structure are预先 designed and implemented before high switching rate operation. This preliminary low-inductance path configuration ensures that when high di/dt currents occur during high-speed switching, the current follows predetermined low-inductance paths, preventing voltage damage while enabling high productivity operation.
Data Source
AI summary
In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection.