Power Leadframe Clip Venting to Reduce Solder Voids

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Solution Overview

Problem

Conventional clip interconnects in electronic devices form solder voids during reflow, leading to increased thermal resistance and reduced electrical conductivity, which degrades device performance.

Innovation Solution

A conductive clip with through-holes and a patterned surface is used to facilitate gas escape during solder reflow, preventing void formation and enhancing heat dissipation and conductivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional clip interconnects are used during solder reflow, then electrical interconnection is achieved, but solder voids form due to trapped gas bubbles, increasing thermal resistance and reducing electrical conductivity

Engineering Contradiction:
Improveelectrical conductivityVSAvoidsolder voids
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The clip interconnect is designed with through-holes penetrating its structure, creating a porous configuration that allows gas bubbles to escape during solder reflow. This porous design prevents solder void formation while maintaining electrical and thermal conductivity, directly resolving the contradiction between achieving reliable interconnection and avoiding harmful voids.

Inventive Principle:
Principle #31Porous materials

Solution Approach 2:

The clip interconnect structure is segmented by introducing through-holes that divide the solid material into regions separated by these channels. This segmentation creates pathways for gas escape, allowing the clip to maintain structural integrity while enabling bubble evacuation during soldering, thus preventing void formation.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If the reflow process is optimized to prevent gas bubble trapping, then solder void formation is reduced, but the process becomes complex and difficult to perform, especially as IC die and clip size increase

Engineering Contradiction:
Improvesolder void preventionVSAvoidreflow process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The clip interconnect structure itself provides the solution by incorporating through-holes that automatically enable gas bubble escape during solder reflow. This self-service design eliminates the need for complex external process controls or optimizations, as the structure inherently facilitates void prevention regardless of reflow process variations or component size increases.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively prevents solder voids, improving thermal and electrical conductivity, thereby enhancing device performance.

Implementation Method 1

Through-holes extend through the first surface of the conductive clip from the depressed floor of the pattern to the second surface of the conductive clip

Methodology Applied
Scientific EffectGas escape through through-holes:

Implementation Method 2

An encapsulating layer covers portions of the first support substrate, second support substrate, IC die, and conductive clip while leaving the first surface of the first portion of the conductive clip exposed to permit heat to radiate away therefrom

Methodology Applied
Scientific EffectThermal radiation: Thermal Radiation

Implementation Method 3

a solder material is used to attach the bottom face of the IC die 5 to the top surface of the die pad 3, the top face of the IC die 5 to the bottom surface of the first portion 7a of the clip 7

Methodology Applied
Scientific EffectSoldering: Soldering

Data Source

PatentEP4345891B1Power leadframe package with reduced solder voids
Publication Date: 2025.09.03 STMICROELECTRONICS INC
  • EP4345891B1 patent drawingFigure 1~4
  • EP4345891B1 patent drawingFigure 5~6
  • EP4345891B1 patent drawingFigure 7

AI summary

An electronic device includes an integrated circuit (IC) with its second face bonded to a first surface of a first support. A conductive clip has a first portion that is elongate and extends across the IC, having its second surface bonded to a first face of the IC by a solder layer. A second portion of the clip extends from the first portion away from the IC toward a second support with the second surface bonded to a first surface of the second support. A first surface of the clip has a pattern formed therein including a depressed floor with fins extending upwardly therefrom. Through-holes extend through the depressed floor to the second surface of the clip. An encapsulating layer covers portions of the first and second supports, IC, and clip while leaving the first surface of the first portion exposed to permit heat to radiate away therefrom.