Leadframe-Less QFN Packaging for PLP Heat Dissipation

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Solution Overview

Problem

Conventional panel level package (PLP) technology is not well suited for manufacturing Quad-Flat No-leads (QFN) packages due to heat draining issues, and reliance on external leadframe suppliers is necessary for current manufacturing methods.

Innovation Solution

Manufacturing QFN packages without external leadframes by using additive manufacturing to form leads and die pads from copper foil laminated on a wafer or panel format substrate, overmolded with molding compound, and creating lead and die pad vias or cavities filled with conductive material, allowing for electrical die-to-lead coupling through methods like wire bonding or laser direct structuring (LDS).

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional leadframe-based QFN packages are used, then manufacturing reliability is maintained, but device complexity and dependency on external suppliers increase

Engineering Contradiction:
Improveinternal manufacturing capabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the leadframe manufacturing function into the semiconductor device fabrication process itself. The substrate serves dual purposes as both the mounting platform and the source of conductive leads, eliminating the need for separate leadframe components and external suppliers.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The substrate is designed to perform multiple functions: it serves as the mechanical support, the electrical connection platform, and the source of conductive leads. This multi-functionality eliminates the need for separate leadframe components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If PLP technology is applied to QFN packages, then productivity increases, but heat draining capability deteriorates

Engineering Contradiction:
Improvemanufacturing throughputVSAvoidheat dissipation efficiency
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The patent applies local quality by creating specific thermal conduction paths at critical locations. The conductive leads are strategically positioned and dimensioned to provide localized heat sinking capability at the die attachment area, while maintaining PLP manufacturing advantages.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent modifies physical parameters of the conductive leads, including their thickness, length, and material composition, to optimize thermal conduction. The leads are designed with sufficient cross-sectional area and conductive material to efficiently drain heat from the die while maintaining compatibility with PLP processes.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Facilitates the production of leadframe-less QFN packages using PLP technology, providing internal manufacturing processes and efficient heat dissipation, while eliminating the need for external leadframe suppliers.

Implementation Method 1

irradiating a molding compound with a laser beam to form cavities or vias

Methodology Applied
Scientific EffectLaser ablation: Laser Ablation

Implementation Method 2

filling the cavities or vias with conductive material, such as by electroplating

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS20250372488A1Method of manufacturing semiconductor devices and corresponding semiconductor device
Publication Date: 2025.12.04 STMICROELECTRONICS INT NV
  • US20250372488A1 patent drawing
  • US20250372488A1 patent drawing
  • US20250372488A1 patent drawing

AI summary

A core pattern of thermally conductive formations and electrically conductive formations is formed extending through an insulating layer laminated onto a carrier foil. A semiconductor chip or die is arranged onto the insulating layer so that the insulating layer supports the semiconductor chip or die and the thermally conductive formations of the core pattern provides a heat propagation path from the semiconductor chip or die and the electrically conductive formations of the core pattern provides contact leads for the semiconductor chip or die. A pattern of further electrically conductive formations is provided to electrically couple the semiconductor chip or die to selected ones of the electrically conductive formations in the core pattern. The carrier foil is removed and singulation is performed to provided individual packaged devices.