Leadframe Semiconductor Package With Recessed Terminals Against Probing

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Solution Overview

Problem

Leadframe chip packages are susceptible to physical probing and hardware hacking due to exposed perimeter lands, posing a risk to sensitive information stored in integrated circuits.

Innovation Solution

A semiconductor package design featuring a die attach pad with lead terminals encapsulated in a molding compound and a step cut through the perimeter of the package, exposing only the outer ends of the lead terminals, which are then shaded by the molding compound, reducing the risk of physical access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If lead terminals are exposed at the perimeter of the package, then electrical connection and ease of assembly are improved, but vulnerability to physical probing and hardware hacking increases

Engineering Contradiction:
Improveease of assemblyVSAvoidvulnerability to physical probing
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent transitions from a planar exposure configuration to a three-dimensional recessed configuration. Lead terminals are arranged in a perimeter pattern and recessed below the package surface, creating vertical dimensionality that maintains electrical connectivity while adding physical security through depth-based protection against probing attacks.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The lead terminals are nested within the package structure by recessing them into the package body. This nesting approach allows the terminals to be contained within the package footprint while still providing external electrical connection, effectively hiding the vulnerable terminal ends within the package's three-dimensional structure.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Object-affected harmful factors

If lead terminals are recessed and shaded, then security against physical probing is improved, but accessibility for electrical connection and assembly may worsen

Engineering Contradiction:
Improvesecurity against physical probingVSAvoidaccessibility for electrical connection
Core Design Contradiction:
Object-affected harmful factorsVSEase of operation

Solution Approach 1:

The patent applies partial recessing rather than complete burial of the lead terminals. The terminals are recessed sufficiently to provide security protection against probing, but not so deeply that they become inaccessible for electrical connection. This partial action optimizes the balance between security and accessibility.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

Different regions of the lead terminals have different exposure levels. The terminal bodies are recessed for security, while the connection ends remain accessible for electrical connection. This local differentiation of quality allows simultaneous optimization of both security and ease of assembly.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP3817033B1Semiconductor package and fabrication method thereof
Publication Date: 2024.09.18 MEDIATEK INC
  • EP3817033B1 patent drawingFigure 1~2
  • EP3817033B1 patent drawingFigure 3~4
  • EP3817033B1 patent drawingFigure 5A~5B

AI summary

A semiconductor package (1) includes a die attach pad (210); a plurality of lead terminals (200) disposed around the die attach pad (210); a semiconductor die (10) mounted on the die attach pad (210); a molding compound (300) encapsulating the plurality of lead terminals (200), the semiconductor die (10), and the die attach pad (210); and a step cut (ST) sawn into the molding compound (300) along a perimeter of a bottom surface (1b) of the semiconductor package (1). The step cut (ST) penetrates through an entire thickness of each of the plurality of lead terminals (200), whereby each of the plurality of lead terminals (200) has at least an exposed outer end (200a) at the step cut (ST).