Semiconductor Package Leadframe Plating for Corrosion Resistance

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Solution Overview

Problem

Existing semiconductor package manufacturing methods face challenges in preventing corrosion of leadframe surfaces exposed during manufacturing, particularly after singulation, as upfront plating of the leadframe leaves un-plated areas susceptible to corrosion, and the use of activators in electroless plating can lead to uncontrolled deposition on encapsulation materials.

Innovation Solution

The method employs an activator-free electroless plating process, specifically the Immersion Silver Immersion Gold (ISIG) process, where semiconductor packages are immersed in silver and gold ion baths without prior activation, ensuring selective plating only on copper leadframe surfaces and avoiding deposition on encapsulation materials, thereby protecting all exposed surfaces and allowing complete plating of contact pads without pre-cuts or activator-induced issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the leadframe is plated up-front as a whole, then the initial surfaces are protected against corrosion, but the surfaces exposed after cuts during manufacturing remain un-plated and susceptible to corrosion

Engineering Contradiction:
Improvecorrosion resistanceVSAvoidplating coverage completeness
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The leadframe is plated with corrosion-resistant material before the singulation cuts are made. This preliminary plating action ensures that all surfaces initially exposed are protected, and the plating layer remains intact through subsequent manufacturing steps, preventing corrosion of surfaces that will later be exposed.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If electroless plating with activators is used, then plating can be applied to the leadframe, but uncontrolled deposition occurs on encapsulation materials

Engineering Contradiction:
Improveplating processabilityVSAvoiduncontrolled plating deposition
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

An activator layer is applied as an intermediary between the leadframe and the plating bath. This activator layer selectively activates only the copper leadframe surfaces while leaving the encapsulation materials inactive, thereby enabling controlled plating deposition only where needed and preventing uncontrolled deposition on non-leadframe surfaces.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in high-quality, long-lasting contact pads resistant to corrosion, with complete plating of contact pad surfaces, ensuring reliable electrical contacts and avoiding plating residuals on encapsulation, thus enhancing manufacturing efficiency and reducing manufacturing costs.

Implementation Method 1

a plating process is applied to the encapsulated leadframe assembly resulting in semiconductor packages having contact pads with at least a plated side face

Methodology Applied
Scientific EffectElectroless plating:

Implementation Method 2

the support lead is separated from the contact pads of the set thereby generating an exposed side face of each contact pad of the set

Methodology Applied
Scientific EffectMechanical cutting/separation:

Data Source

PatentEP3355348B1Method for manufacturing a semiconductor package
Publication Date: 2021.06.23 SENSIRION AG
  • EP3355348B1 patent drawingFigure 1~2
  • EP3355348B1 patent drawingFigure 3
  • EP3355348B1 patent drawingFigure 4a~5

AI summary

In a method for manufacturing a semiconductor package an electrically conducting leadframe (2) is provided including a front side (fs) and a back side (bs), and including a die pad (21), a set of contact pads (22) and a support lead (24) connected to the contact pads (22) of the set. A semiconductor chip (3) is mounted on the front side (fs) of the die pad (21) resulting in a leadframe assembly (4). The leadframe assembly (4) is at least partially encapsulated. The support lead (24) is separated from the contact pads (22) thereby generating at least an exposed side face (sf) of each contact pad (22). An electroless immersion plating process is applied resulting in a semiconductor package (10) having contact pads (22) with at least a side face (sf) each plated with a silver plating (81) and a gold plating (82) on top of the silver plating (81).