Leadframe Routing for Multi-Chip Power Package Interconnections
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Solution Overview
Problem
The challenge in multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor packages is to efficiently design and fabricate complex electrical interconnections without wire shorting, while maintaining cost-effectiveness and reliability, especially in larger form factors like 12 mm by 12 mm, where single-layer leadframes limit routing and increase the risk of package cracking.
Innovation Solution
A multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections, with a copper alloy for high thermal and electrical conductivity, and selective plating for enhanced adhesion, allows for efficient routing through the leadframe to avoid wire crossing and shorting, using thicker copper wires for power connections and gold wirebonds for gate connections, and a thin mold compound to maintain package reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer leadframe is used for electrical interconnections, then the fabrication cost is reduced, but the wiring complexity increases and the risk of wire shorting increases
Solution Approach 1:
The patent transitions from planar wire routing to three-dimensional leadframe routing. Electrical connections are established by routing wires through multiple layers of the leadframe structure (top surface, sidewalls, bottom surface) rather than across a single plane, enabling complex interconnections without increasing wiring complexity on any single layer.
Solution Approach 2:
The leadframe serves as an intermediary structure that provides pre-formed conductive pathways and mounting surfaces. Instead of directly routing wires between components, the leadframe acts as a mediator with integrated routing channels and connection points that simplify the wiring process and reduce the risk of shorting.
2Reliability
If wire layouts are designed to prevent wire shorting, then electrical reliability is improved, but the design complexity and fabrication difficulty increase
Solution Approach 1:
The patent eliminates wire crossing and shorting risks by routing connections through three-dimensional space using the leadframe structure. Wires are guided through vertical channels and lateral pathways within the leadframe rather than across a two-dimensional plane, naturally preventing intersections and shorting without complex planar design rules.
Solution Approach 2:
The leadframe structure itself provides the routing pathways and physical separation needed to prevent wire shorting. The geometry of the leadframe (sidewalls, layers, and integrated routing channels) automatically guides wire placement and maintains safe distances between conductors, making the system self-regulating rather than requiring external design constraints.
3Reliability
If package thickness is increased to reduce wire shorting risks, then electrical reliability is improved, but the risk of package cracking increases
Solution Approach 1:
The patent achieves electrical isolation and routing separation through lateral leadframe structures and multi-level pathways rather than increasing vertical thickness. The leadframe extends horizontally with integrated routing channels that provide safe wire separation without requiring a thicker package body, thus maintaining mechanical strength while ensuring electrical reliability.
4Ease of manufacture
If a simple leadframe is used instead of multilayered substrates, then fabrication cost is reduced, but electrical wiring and routing becomes more challenging
Solution Approach 1:
The leadframe is designed to perform multiple functions simultaneously: it provides structural support for mounting semiconductor chips, offers pre-formed conductive pathways for electrical connections, and serves as a heat sink for thermal management. This multi-functionality eliminates the need for separate multilayered substrate structures while maintaining ease of wiring and routing.
Solution Approach 2:
The patent utilizes the three-dimensional structure of the leadframe (top surface, sidewalls, bottom surface, and internal channels) to provide routing pathways that are inherently integrated into the support structure. This eliminates the need for separate multilayered substrates while maintaining ease of wiring, as the routing paths are built-in rather than added.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient electrical and thermal conductivity, enhanced reliability, and cost-effective fabrication by using the leadframe as a routing apparatus, reducing the risk of wire shorting and package cracking, while maintaining a compact form factor and high power density performance.
Implementation Method 1
utilizing a leadframe for electrical interconnections, with a copper alloy for high thermal and electrical conductivity
Implementation Method 2
utilizing a leadframe for electrical interconnections, with a copper alloy for high thermal and electrical conductivity
Implementation Method 3
selective plating for enhanced adhesion
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.