Leadframe Sidewall Plating for Wettable Flank Packages
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Solution Overview
Problem
Conventional methods for manufacturing leadless semiconductor die packages with wettable flanks are complex and do not allow for targeted plating of specific surfaces, making it difficult to ensure proper solder connections.
Innovation Solution
A method involving a lead frame with integrated circuit dies, where the bottom surfaces are initially plated, and then channels are created to expose the sidewalls for additional plating, allowing for separate plating of bottom and sidewall surfaces with different materials to enhance wettable properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple surfaces are plated at the same time with the same plating material, then the plating process is simpler, but targeted plating for specific surfaces is not achieved
Solution Approach 1:
The patent divides the plating process into separate sequential steps: first plating the bottom surface, then creating channels to expose sidewalls, and finally plating the sidewalls. This segmentation allows each surface to be plated independently with appropriate materials, resolving the contradiction between process simplicity and targeted plating capability.
Solution Approach 2:
The patent applies preliminary plating to the bottom surface before creating channels to expose the sidewalls. This preliminary action ensures the bottom surface is properly plated first, then subsequent steps expose and plate the sidewalls with different materials, achieving targeted plating while maintaining process organization.
2Reliability
If conventional step cutting process is used to form wettable flanks, then multiple surfaces can be plated, but the process is complicated and does not allow targeted plating
Solution Approach 1:
Instead of using complex step cutting to expose sidewalls, the patent segments the plating process into separate steps and uses channel creation through the mold encapsulation to expose sidewalls for plating. This reduces manufacturing complexity while maintaining the ability to create wettable flanks for reliable solder connections.
Solution Approach 2:
The patent introduces channels as an intermediary structure that cuts through the mold encapsulation to expose the sidewalls of the leads. This intermediary approach allows sidewall plating without requiring complex step cutting of the leads themselves, simplifying the overall manufacturing process while achieving the same functional result.
3Manufacturing precision
If channels are created to expose sidewalls for separate plating, then targeted surface treatment is enabled, but the manufacturing process becomes more complex
Solution Approach 1:
The channels act as an intermediary mechanism that provides precise access to the sidewalls for plating. Rather than directly complicating the plating process, the channels serve as a controlled pathway that enables precise surface treatment of specific areas (sidewalls) while keeping the plating steps themselves relatively simple.
Solution Approach 2:
The patent introduces a vertical dimension by creating channels that cut through the mold encapsulation from the top surface down to expose the sidewalls. This dimensional approach allows precise access to sidewalls for plating without requiring complex lateral manipulation or multiple plating fixtures, thereby enabling targeted treatment with moderate process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the plating process, enables targeted surface treatment, and improves the wettable properties of the semiconductor die packages, facilitating better solder connections and inspection.
Implementation Method 1
The bottom surface of the plurality of leads may be plated with a first electrical plating
Implementation Method 2
The first lead sidewall and the second lead sidewall may be plated, through the channel, with a second electrical plating
Data Source
AI summary
Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame assembly may include a plurality of leads, each lead including a die surface and a plating surface, and an integrated circuit die arranged on the die surface. The plating surface for each of the leads may be plated with an electrical plating. A connecting film may be applied and lead frame assembly may be singulated into individual semiconductor packages by a series of cuts through each of the plurality of leads and the electrical plating of each of the plurality of leads to a depth up to or through a portion of the connecting film to create a channel exposing lead sidewalls of each of the plurality of leads. The lead sidewalls of each of the plurality of leads may be plated with a second electrical plating and the connecting film may be removed.