Semiconductor Leadframe Solder Dam Protrusion Design
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Solution Overview
Problem
Existing semiconductor packages face challenges in effectively isolating and protecting switching elements like MOSFETs and IGBTs, particularly in preventing solder flow between islands and ensuring accurate detection of overcurrent and short-circuit conditions due to variations in on-resistance of charging and discharging FETs.
Innovation Solution
The implementation of a leadframe design with tie bars having protrusions and a slit between islands, along with a battery protection IC that includes a fuse array and latches, allows for electrical isolation and accurate detection of overcurrent and short-circuit conditions by generating a threshold voltage for comparators, and automatic fuse refreshing to maintain accurate latch states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If tie bars are used to couple islands, then structural integrity is improved, but solder flow between islands occurs
Solution Approach 1:
The tie bar is designed with a protrusion at its center that creates a local barrier to solder flow. This protrusion extends upward from the leadframe surface to form a solder dam, preventing solder from flowing between islands while the rest of the tie bar maintains structural coupling. This local modification resolves the contradiction by adding solder flow prevention capability without compromising the overall structural integrity of the tie bar.
2Area of stationary object
If islands are placed close together, then package area is reduced, but solder shorting between islands increases
Solution Approach 1:
The protrusion on the tie bar acts as an intermediary barrier between adjacent islands. It creates a physical obstruction that prevents solder from flowing directly from one island to another, allowing islands to be placed closer together without increasing the risk of solder shorting. This intermediary structure enables compact packaging while maintaining electrical isolation between islands.
3Measurement precision
If on-resistance of FETs varies, then detection accuracy of overcurrent conditions deteriorates, but system complexity increases with fuse array and latches
Solution Approach 1:
The fuse array and latches are pre-configured to represent different on-resistance states of the FETs. By having multiple fuses that can be selectively blown during manufacturing, the system establishes predetermined threshold voltages that correspond to various FET on-resistance values. This preliminary configuration allows the overcurrent detection circuit to accurately detect overcurrent conditions despite FET parameter variations, without requiring complex real-time adjustment mechanisms.
Solution Approach 2:
The system uses multiple fuses with different resistance values to create a range of threshold voltages for overcurrent detection. By changing the combination of blown and unblown fuses, the threshold voltage can be adjusted to match the actual on-resistance of the FETs. This parameter variation approach allows accurate detection across different FET specifications while using a relatively simple hardware structure.
Data Source
AI summary
A semiconductor package includes a leadframe having a first island and second island each having an upper surface corresponding with an upper surface of the leadframe. One or more tie bars couple the first island with the second island. At least one tie bar has a protrusion extending from the upper surface of the leadframe and configured to substantially prevent a flow of a solder between the first and second islands. A first die couples with the leadframe at the first island and a second die couples with the leadframe at the second island. At least one of the tie bars has a recess at a lower surface of the leadframe. The leadframe includes a slit between the first and second island.