Leadframe Submodule With Expanded Contact Elements

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Solution Overview

Problem

Conventional approaches for embedding semiconductor chips in printed circuit board (PCB) devices are cumbersome and complex, involving sensitive process steps that make them impractical.

Innovation Solution

The electronic module features a circuit board or leadframe with recess areas housing electronic sub-modules, each comprising a semiconductor chip and encapsulation material, where the contact elements have a larger surface area than the contact pads, facilitating easier fabrication and electrical connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional approaches for embedding semiconductor chips in PCB devices are used, then electrical connectivity is achieved, but the process becomes cumbersome and complex with sensitive process steps

Engineering Contradiction:
Improveelectrical connectivityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention divides the embedding process into separate stages: first creating recess areas in the PCB carrier, then placing pre-packaged semiconductor chips into these recesses, and finally filling the remaining space with dielectric material. This segmentation simplifies the overall process by eliminating complex simultaneous operations and sensitive process steps while ensuring reliable electrical connectivity through the leadframe structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The semiconductor chips are pre-packaged with their encapsulation material and contact elements before being placed in the PCB recess areas. This preliminary packaging action simplifies the embedding process by eliminating the need for complex on-site packaging operations and sensitive process steps, while maintaining reliable electrical connectivity through the pre-formed contact elements.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If conventional embedding techniques are used, then semiconductor chips are embedded in PCB, but the process is cumbersome and sometimes impractical

Engineering Contradiction:
Improveembedding processVSAvoidfabrication time
Core Design Contradiction:
Ease of manufactureVSLoss of time

Solution Approach 1:

The embedding process is segmented into independent steps: recess preparation, chip placement, and dielectric filling. This segmentation makes each step simpler and more manageable, improving ease of manufacture while reducing overall fabrication time by eliminating complex simultaneous operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The encapsulation material in the pre-packaged semiconductor chips serves multiple functions automatically: it protects the chip, provides structural support, and facilitates thermal management. This self-service approach eliminates the need for additional separate operations, simplifying the manufacturing process and reducing fabrication time.

Inventive Principle:
Principle #25Self-service

3Reliability

If contact elements with larger surface area than contact pads are used, then electrical connectivity is enhanced, but the spatial arrangement becomes more complex

Engineering Contradiction:
Improveelectrical connectivityVSAvoidspatial arrangement
Core Design Contradiction:
ReliabilityVSShape

Solution Approach 1:

The contact elements are designed to extend laterally beyond the contact pads in the horizontal plane, utilizing the available space in the recess areas. This dimensional approach enhances electrical connectivity through increased surface area while maintaining a simple vertical stacking arrangement, avoiding complex spatial configurations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10304751B2Electronic sub-module including a leadframe and a semiconductor chip disposed on the leadframe
Publication Date: 2019.05.28 INFINEON TECHNOLOGIES AG
  • US10304751B2 patent drawing
  • US10304751B2 patent drawing
  • US10304751B2 patent drawing

AI summary

An electronic sub-module includes a leadframe, a semiconductor chip disposed on the leadframe and an encapsulation material disposed on the leadframe and on the semiconductor chip. The semiconductor chip has a first contact pad on a first main face of the semiconductor chip. The sub-module also includes a first contact element on a first main face of the electronic sub-module. The first contact element is electrically connected with the first contact pad. A surface area of the first contact element is greater than a surface area of the first contact pad.