Leadframe Vertical Interconnect FO-WLCSP
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Solution Overview
Problem
The formation of conductive vias in fan-out wafer level chip scale packages (FO-WLCSPs) increases manufacturing time and costs while reducing reliability due to the propensity for defects in vertical electrical interconnects.
Innovation Solution
The use of a leadframe disposed between the semiconductor die to form a vertical interconnect, eliminating the need for conductive vias and improving manufacturing efficiency and reliability by providing a direct electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive vias are formed through the encapsulant for vertical electrical interconnect, then electrical connection between topside and bottom side build-up interconnect structures is achieved, but manufacturing time increases and reliability decreases due to defects in via formation
Solution Approach 1:
The patent removes the problematic conductive via formation step from the manufacturing process. Instead of forming vias through the encapsulant, the invention uses an embedded leadframe structure that provides vertical interconnect pathways during the molding process itself, eliminating the subsequent via drilling, cleaning, and filling operations that consume time and introduce defects
Solution Approach 2:
The leadframe is pre-positioned and embedded in the encapsulant during the molding process before other components are assembled. This preliminary action creates the vertical interconnect pathways in advance, eliminating the need for later via formation steps and enabling direct electrical connection between interconnect structures
2Reliability
If conductive vias are formed through the encapsulant, then vertical electrical interconnect is achieved, but manufacturing costs increase due to additional process steps
Solution Approach 1:
The patent extracts the via formation operations from the manufacturing sequence, removing the costly steps of drilling, cleaning, and filling conductive vias. The leadframe-based approach provides the same vertical interconnect function through a simpler, more cost-effective process that integrates into the molding operation
Solution Approach 2:
The leadframe serves as a temporary but effective solution during manufacturing - it provides the necessary vertical interconnect pathways during assembly and can be easily integrated into the encapsulant structure, replacing expensive and complex via formation processes with a more economical approach
Data Source
AI summary
A semiconductor device has a plurality of semiconductor die or components mounted over a carrier. A leadframe is mounted over the carrier between the semiconductor die. The leadframe has a plate and bodies extending from the plate. The bodies of the leadframe are disposed around a perimeter of the semiconductor die. An encapsulant is deposited over the carrier, leadframe, and semiconductor die. A plurality of conductive vias is formed through the encapsulant and electrically connected to the bodies of the leadframe and contact pads on the semiconductor die. An interconnect structure is formed over the encapsulant and electrically connected to the conductive vias. A first channel is formed through the interconnect structure, encapsulant, leadframe, and partially through the carrier. The carrier is removed to singulate the semiconductor die. A second channel is formed through the plate of the leadframe to physically separate the bodies of the leadframe.