Leadframeless Chip Packaging via Conductive Adhesive
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Solution Overview
Problem
Conventional electronic chip packaging methods involve high temperature soldering and mechanical stress, which can damage sensitive chips and are cumbersome and unreliable.
Innovation Solution
A method of packaging electronic chips using a substrate with an electrically conductive frame, where chips are placed in cavities within the frame and encapsulated with a conductive material, forming vias for electrical connections without the need for soldering, allowing for batch processing and reduced stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional soldering methods are used to connect electronic chips to leadframe, then electrical connection is achieved, but high temperature and mechanical stress damage the sensitive chips
Solution Approach 1:
The patent extracts the harmful soldering process from the chip connection method. Instead of soldering chips to leadframe, the invention uses a leadframeless architecture where chips are mounted on a substrate and electrically connected through conductive adhesive applied to pad structures on the substrate, eliminating high temperature and mechanical stress exposure
Solution Approach 2:
The patent introduces conductive adhesive as an intermediary material between the chip electrodes and the substrate pad structures. This conductive adhesive provides both mechanical bonding and electrical connection without requiring high temperature soldering, thus protecting sensitive chips from thermal and mechanical stress while achieving reliable electrical connection
2Reliability
If individual chip packaging is performed, then each chip can be processed carefully, but the processing time and complexity increase significantly
Solution Approach 1:
The patent merges multiple individual chip packaging operations into a single batch processing step. Multiple chips are mounted simultaneously on the substrate in their respective cavities, and the conductive adhesive is applied in a single operation to all chips at once, enabling parallel processing that significantly increases throughput while maintaining consistent quality across all chips
Solution Approach 2:
The substrate structure with integrated cavities and pad structures serves multiple functions simultaneously: it provides mechanical support for multiple chips, defines precise mounting positions through cavities, provides electrical connection paths through pad structures, and enables batch processing. This multi-functional design allows reliable packaging of multiple chips in a single operation
Data Source
AI summary
A method which comprises arranging a plurality of electronic chips in a plurality of chip accommodation cavities each defined by a respective surface portion of a substrate and a wall delimited by a respective one of a plurality of holes in an electrically conductive frame arranged on the substrate, at least partially encapsulating the electronic chips in the chip accommodation cavities by an encapsulant, and forming electrically conductive contacts for electrically contacting the at least partially encapsulated electronic chips.