Leadless Discrete Component Packaging for Smaller Semiconductor Footprints
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Solution Overview
Problem
Conventional semiconductor packaging using surface mount technology (SMT) components requires significant space due to the need for leads and clearances, making it challenging to create compact packages, especially when multiple discrete components are involved.
Innovation Solution
Employing leadless discrete components that can be flexibly positioned on the substrate without leads, using various coupling methods such as wire bonding, clips, or direct connections, allowing for more compact designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional SMT components with leads are used, then electrical connectivity is achieved, but package size increases significantly
Solution Approach 1:
The patent removes the lead structure from discrete components, extracting only the essential functional element (the component body) and connecting it directly to the substrate. This eliminates the need for leads and associated clearance spaces, directly resolving the contradiction between package size and electrical connectivity.
Solution Approach 2:
The patent transitions from a planar layout requiring lead extensions to a three-dimensional stacked configuration where components are vertically positioned on the substrate. This dimensional change allows electrical connections to be made through vertical vias rather than horizontal lead extensions, dramatically reducing the horizontal package footprint.
2Adaptability or versatility
If multiple discrete components are placed on substrate, then functionality is enhanced, but substrate area increases
Solution Approach 1:
The patent implements a stacked configuration where multiple discrete components are vertically arranged one above another on the substrate, similar to nested dolls. This vertical nesting allows multiple components to occupy the same horizontal footprint, enhancing circuit functionality while minimizing substrate area consumption.
Solution Approach 2:
The patent exploits the vertical dimension to accommodate multiple discrete components that would otherwise require horizontal space. By stacking components vertically and using through-substrate vias for interconnections, the design achieves enhanced functionality without proportionally increasing substrate area.
3Volume of moving object
If leadless discrete components are used, then package size is reduced, but electrical connection methods become more complex
Solution Approach 1:
The patent merges the discrete component body directly with the substrate surface, eliminating the separate lead connection step. The component is positioned and bonded directly to the substrate, with electrical connections made through vias that pass through the substrate to contact the component's bottom surface, simplifying the overall assembly process despite the leadless design.
Solution Approach 2:
The patent introduces through-substrate vias as intermediary conductive pathways that connect the bottom surface of leadless components to underlying substrate traces. This intermediary structure provides a reliable electrical connection method that is actually simpler than managing flexible leads, as the vias are formed during substrate fabrication.
4Quantity of substance
If components are closely spaced, then package density increases, but heat dissipation becomes more challenging
Solution Approach 1:
The patent incorporates thermal vias within the substrate structure that automatically conduct heat away from densely packed components. The substrate itself serves as a heat dissipation system, with integrated thermal pathways that passively manage thermal loads without requiring additional active cooling components, thus enabling high component density while maintaining acceptable temperature levels.
Data Source
AI summary
An illustrative apparatus may include a substrate having a first portion and a second portion that is electrically isolated from the first portion. The apparatus may further include a leadless discrete component and a semiconductor die. The leadless discrete component may have a first surface and a second surface opposite the first surface, the first surface being physically coupled and electrically coupled to the first portion of the substrate, and the semiconductor die may be physically coupled and electrically coupled to the second portion of the substrate. The apparatus may further include a plurality of leads including a first lead electrically coupled to the first portion of the substrate, a second lead electrically coupled to the second portion of the substrate, and a third lead electrically coupled to the second surface of the leadless discrete component. Corresponding apparatuses and methods are also disclosed.