Leadless IC Packaging via Substrate Removal and Tiered Pads
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Solution Overview
Problem
Conventional integrated circuit packaging technologies face challenges in reducing package size while increasing input/output connections, leading to issues like signal interference, assembly difficulties, and cost concerns, particularly with grid array devices that are prone to warping and cracking.
Innovation Solution
A leadless integrated circuit packaging system is developed, featuring a substrate with a die attach pad and a tiered plated pad array, where an integrated circuit die is mounted and electrically interconnected, followed by a molded package body formation, and the substrate is removed to expose contact pads, allowing for a more compact and reliable connection structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of I/O connections is increased while decreasing package size, then connection density is improved, but signal interference and cross-talk increase
Solution Approach 1:
The patent transitions from two-dimensional peripheral lead arrangement (QFP) to three-dimensional vertical plated through-holes. By drilling holes through the substrate thickness and plating them, connections are distributed in the vertical dimension rather than compressed along the perimeter, reducing lateral lead density and associated signal interference while increasing total connection capacity.
Solution Approach 2:
The substrate acts as an intermediary structure that distributes I/O connections through its thickness. Instead of leads running laterally close together, the substrate provides a three-dimensional pathway where signals travel through isolated vertical channels, reducing electromagnetic coupling and cross-talk between adjacent connections.
2Quantity of substance
If the pitch between adjacent leads is reduced to increase connection density, then number of I/O connections is improved, but manufacturing difficulty increases
Solution Approach 1:
The invention moves lead connections from the lateral plane to the vertical dimension by drilling through-substrate holes. This allows pitch to be determined by hole diameter and spacing rather than lateral lead width, enabling finer effective pitch without proportionally reducing lateral dimensions, thus maintaining manufacturability while increasing connection density.
3Quantity of substance
If circuit board interposers are used to increase I/O connections, then connection capacity is improved, but package size and cost increase
Solution Approach 1:
The patent extracts and eliminates the separate circuit board interposer layer used in BGA packages. Instead of requiring a distinct PCB substrate, the I/O connections are directly formed in the IC package substrate itself through plated through-holes, integrating the interposer function into the package structure and reducing overall package size and cost.
Solution Approach 2:
The invention merges the functions of the IC package substrate and the circuit board interposer into a single substrate structure. The plated through-holes provide both the mechanical support and electrical connection functions that would otherwise require separate layers, consolidating the structure and reducing package footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces package size and height, minimizes warping, and lowers costs by eliminating the need for a lead frame, while maintaining high integration density and performance.
Implementation Method 1
coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array
Implementation Method 2
forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array
Data Source
AI summary
A method of manufacture of a leadless integrated circuit packaging system includes: providing a substrate; patterning a die attach pad on the substrate; forming a tiered plated pad array around the die attach pad; mounting an integrated circuit die on the die attach pad; coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array; forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and exposing a contact pad layer by removing the substrate.