Leadless Multi-Chip Module Layout for Isolation and Thermal Dissipation
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Solution Overview
Problem
Existing multi-chip module (MCM) packages face challenges in achieving high power density and miniaturization while maintaining sufficient isolation and thermal management, particularly in DC/DC telecom brick modules where high working voltages and high-frequency operations require large spacing between lead terminals, leaving limited room for thermal pads.
Innovation Solution
The proposed MCM leadless package design includes a Tx/signal coding die and at least one Rx/driver die with die-to-die wire bonding and a high-voltage isolator device in the signal path. This design utilizes a leadless leadframe with half-etched lead terminals and thermal pads for direct thermal connection to a PCB, enhancing creepage distance and thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large spacing is provided between lead terminals to meet isolation requirements for high voltage operation, then reliability is improved, but the package area increases and power density decreases
Solution Approach 1:
The patent transitions from a conventional planar package layout to a three-dimensional stacked architecture where multiple IC dies are vertically positioned on top of each other. This vertical stacking enables signal and power pathways to extend in the Z-dimension, allowing sufficient electrical isolation in the horizontal plane while maintaining a compact footprint. The half-etched lead terminals further exploit this by having different thickness profiles that provide isolation in multiple dimensions simultaneously.
Solution Approach 2:
The patent implements nested positioning where one IC die is placed directly on top of another die within the same package. The lower die contains high-voltage circuitry while the upper die contains low-voltage circuitry, creating a nested vertical arrangement. This nesting allows high-voltage isolation requirements to be met through vertical separation rather than horizontal spacing, thereby reducing the overall package area while maintaining reliability.
2Reliability
If large spacing is provided between lead terminals for high voltage isolation, then reliability is improved, but power density decreases
Solution Approach 1:
By moving the isolation strategy into the vertical dimension through stacked die arrangement, the horizontal space is freed up for higher power density. The power pathways and signal pathways can be densely packed in the horizontal plane while maintaining isolation through vertical separation and half-etched terminal structures.
Solution Approach 2:
The nested vertical stacking of high-voltage and low-voltage dies allows both isolation and high power density to coexist. The lower die handles high-voltage power conversion while the upper die handles control signals, creating efficient power pathways vertically while maintaining compact horizontal dimensions for high power density.
3Reliability
If sufficient spacing is provided between channels, then reliability is improved, but the package area increases
Solution Approach 1:
The patent positions different functional channels in the vertical dimension rather than spreading them horizontally. Multiple channels can be routed through different layers of stacked dies, allowing channel-to-channel isolation to be achieved through vertical separation. This enables compact horizontal packaging while maintaining adequate isolation distances for reliability.
4Productivity
If miniaturization is pursued to reduce package size, then productivity is improved, but thermal management becomes more difficult
Solution Approach 1:
The patent extracts the thermal management function by providing a separately accessible thermal pad that is thermally coupled to the IC dies through the leadframe structure. This dedicated thermal pathway allows efficient heat extraction from the compact stacked architecture without interfering with the miniaturized horizontal footprint. The thermal pad can be directly bonded to heat sinks or cooling structures.
5Temperature
If thermal pad area is increased for better thermal management, then temperature control is improved, but the package area increases
Solution Approach 1:
The thermal management function is moved to the vertical dimension through the stacked die architecture. Heat generated in the upper die can conduct directly to the lower die and through to the thermal pad, creating efficient vertical thermal pathways. This allows adequate thermal management without requiring large horizontal thermal pad areas, as the heat flow exploits the Z-dimension for efficient heat sinking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a compact MCM package with increased external creepage distance and improved thermal management, enabling higher power dissipation and operation at higher frequencies and temperatures, while meeting stringent isolation requirements.
Implementation Method 1
at least one of the die includes at least one high voltage isolation (HV ISO) device, such as a HV capacitor, connected in series in the data channel path. This arrangement enables modulated data signals generated on the Tx die to be passed to the Rx die, but blocks high voltage (e.g., 500 or 1,000 volts during a surge) applied to the active circuitry on the Rx die
Implementation Method 2
The MCM package can include a first thermal pad and a second thermal pad, each respectively underlying a corresponding one of the first and second IC die. The thermal pads enable direct thermal connection to a PCB, enhancing thermal dissipation and enabling operation at higher frequencies and temperatures
Implementation Method 3
Electrical connections between the respective IC die when laterally positioned on die pads within a MCM generally include bond wires connecting to inner located bond pads on the respective IC die including die-to-die bond wires
Data Source
AI summary
A multi-chip module (MCM) package includes a leadframe including half-etched lead terminals including a full-thickness and half-etched portion, and second lead terminals including a thermal pad(s). A first die is attached by a dielectric die attach material to the half-etched lead terminals. The first die includes first bond pads coupled to first circuitry configured for receiving a control signal and for outputting a coded signal and a transmitter. The second die includes second bond pads coupled to second circuitry configured for a receiver with a gate driver. The second die is attached by a conductive die attach material to the thermal pad. Bond wires include die-to-die bond wires between a portion of the first and second bond pads. A high-voltage isolation device is between the transmitter and receiver. A mold compound encapsulates the first and the second die.