Leadless Pacemaker Event Data Storage via Hardware Logic
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Solution Overview
Problem
Traditional pacemakers face high energy consumption and increased size due to CPU-centric data collection and storage methods, which impact service time and volume, especially when handling frequent cardiac events.
Innovation Solution
A leadless pacemaker design utilizing dedicated logic circuits and hardware event counters that operate independently of the CPU, allowing for efficient event data generation and storage without invoking CPU operations, using a central processing unit to transfer overflow bits to RAM event counters for data accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If CPU-centric approach is used to collect and store event data, then data processing and analysis capability is improved, but energy consumption increases and service time decreases
Solution Approach 1:
The patent segments the event data processing function by introducing dedicated hardware logic circuits that operate independently from the CPU. These logic circuits are specifically designed to generate event data and manage hardware event counters, separating this function from the general-purpose CPU to reduce CPU energy consumption while maintaining data processing capability.
Solution Approach 2:
The hardware event counters and logic circuits operate autonomously without requiring continuous CPU intervention. The system self-manages event counting and data storage through dedicated hardware pathways, eliminating the need for CPU to wake from low-power states frequently, thus reducing overall energy consumption.
2Loss of information
If CPU-centric approach is used to handle frequent cardiac events, then event data storage is achieved, but pacemaker volume increases
Solution Approach 1:
The patent divides the data handling system into separate functional blocks: dedicated logic circuits for event detection, hardware event counters for data accumulation, and RAM for storage. This segmentation allows each component to be optimized for its specific function, reducing the overall footprint compared to a monolithic CPU-centric approach.
Solution Approach 2:
The patent extracts the event data collection and counting functionality from the CPU and implements it as dedicated hardware logic. This extraction reduces the computational burden on the CPU and allows for a more compact design since the extracted functions can be implemented with simpler, smaller hardware components.
3Measurement precision
If CPU is kept active to handle timing measurements and event processing, then measurement precision is improved, but energy consumption increases
Solution Approach 1:
The patent segments timing measurement functions into dedicated hardware circuits that operate independently of the CPU. These circuits can perform precise timing measurements continuously without requiring CPU activation, thereby maintaining measurement precision while significantly reducing CPU energy consumption.
Solution Approach 2:
The dedicated timing circuits and hardware counters operate continuously in the background without requiring CPU intervention. This continuous operation maintains accurate timing measurements and event counting while the CPU remains in low-power states, achieving both precision and energy efficiency.
Data Source
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AI summary
The invention relates to a leadless pacemaker (1) comprising a central processing unit (2), a first logic circuit (11) configured to generate event data based on a first event (E1) occurring during operation of the leadless pacemaker (1), a first hardware event counter (21) configured to be incremented if specific event data are generated by said first logic circuit (11), a first memory unit (30) comprising a first bit configured to be set if said first hardware event counter (21) is incremented to a first maximum number of counts, a second memory unit (40) communicating with said first memory unit (30), wherein said central processing unit (2) is configured to transfer said first bit to said second memory unit (40), a first RAM event counter (51) in a random access memory of said leadless pacemaker (1), wherein said central processing unit (2) is configured to increment said first RAM event counter (51) if said first bit is transferred to the second memory unit (40). The invention further relates to a method for storing event data in a leadless pacemaker (1).