Leadless Semiconductor Package Metal Side Pad Inspection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Leadless packaged semiconductor devices are difficult to inspect for solder joint defects due to hidden I/O terminals, and conventional inspection methods like Automated Optical Inspection (AOI) are not effective, while Automatic X-Ray Inspection (AXI) is expensive. Additionally, forming metal side pads to facilitate inspection can be challenging for devices with specific terminal arrangements.
Innovation Solution
The method involves providing sacrificial bond wires to maintain electrical continuity between lead frame sub-structures, allowing for electroplating of metal side pads, which are then used to enable optical inspection. This includes a first series of parallel cuts to expose terminals, electroplating, and a second series of angled cuts to singulate the device, ensuring electrical isolation and preventing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If I/O terminals are arranged on the bottom of the device for leadless packaging, then package thickness and footprint are reduced, but inspection of solder joints becomes difficult
Solution Approach 1:
The patent extends metal side pads from the bottom I/O terminals up the external sidewalls of the device, transforming the inspection problem from a two-dimensional bottom view to a three-dimensional structure where solder joints become visible from the side, enabling AOI inspection while maintaining the leadless package's thin profile
2Difficulty of detecting and measuring
If metal side pads are formed to enable AOI inspection, then solder joint inspection becomes possible, but the electroplating process becomes complex for devices with isolated terminals
Solution Approach 1:
The patent performs the first series of parallel cuts before electroplating to expose the side portions of terminals, and maintains electrical continuity during electroplating by keeping terminals connected to the leadframe structure. This preliminary preparation simplifies the subsequent electroplating process and enables uniform metal side pad formation
Solution Approach 2:
The patent uses the leadframe structure as an intermediary electrical conductor that maintains electrical continuity between multiple I/O terminals during the electroplating process, allowing uniform metal side pad formation on all terminals simultaneously even when terminals are spatially separated
3Productivity
If parallel row cuts are made first to define rows, then columns are separated, but middle I/O terminals become electrically isolated, preventing metal side pad formation
Solution Approach 1:
The patent performs the first series of parallel row cuts before electroplating to define rows, but maintains electrical continuity through the leadframe structure. The electroplating step is performed while terminals remain electrically connected, enabling metal side pad formation before final singulation separates the columns
Solution Approach 2:
The patent maintains electrical continuity between I/O terminals and the leadframe structure throughout the manufacturing process, including during and after the first series of parallel cuts. This continuous electrical connection enables the electroplating process to form metal side pads on all terminals uniformly, even when terminals are spatially separated by the row cuts
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for effective optical inspection of solder joints and improves mechanical stability and shearing performance by forming metal side pads on leadless semiconductor devices, making them amenable to AOI while maintaining electrical integrity.
Implementation Method 1
electro-plating said terminals to form metal side pads
Data Source
AI summary
A method of forming semiconductor devices on a leadframe structure. The leadframe structure comprising an array of leadframe sub-structures each having a semiconductor die arranged thereon. The method comprises; providing electrical connections between terminals of said lead frame sub-structures and said leadframe structure; encapsulating said leadframe structure, said electrical connections and said terminals in an encapsulation layer; performing a first series of parallel cuts extending through the leadframe structure and the encapsulation layer to expose a side portion of said terminals; electro-plating said terminals to form metal side pads; and performing a second series of parallel cuts angled with respect to the first series of parallel cuts, the second series of cuts extending through the lead frame structure and the encapsulation layer to singulate a semiconductor device from the leadframe structure.