Leadless Semiconductor Package Side-Flank Plating for Solder Wetting

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Solution Overview

Problem

Leadless semiconductor packages face challenges in achieving full plating of side flanks, which are non-wettable due to untreated copper surfaces, affecting solderability and inspection of solder joints, especially in leadless packages like DFN and QFN.

Innovation Solution

A method involving conductive substrates like conductive tape or glue is applied to leadless packages to facilitate electro-plating of side flanks, followed by precise cutting to achieve full plating of all sides, ensuring solder wettable surfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional electro-plating is used on leadless packages, then the copper surface is plated, but the side flanks remain non-wettable due to untreated surfaces

Engineering Contradiction:
ImprovesolderabilityVSAvoidplating coverage
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The method applies preliminary actions by performing selective cutting to expose side flanks before plating, and using conductive substrate to prepare the surface for electro-plating. The conductive substrate is applied to the package body, and side flanks are cut to expose fresh copper surfaces that will be plated, ensuring complete coverage including areas that would otherwise remain untreated.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The cutting process is segmented into multiple steps: first cutting to expose side flanks, then plating, and potentially second cutting to achieve final dimensions. This segmentation allows different portions of the package to receive different treatments - the side flanks are exposed and plated separately from the bottom surface, ensuring complete plating coverage on all surfaces that require solderability.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If side flanks are left flush with mold compound, then package structure is simple, but solder cannot climb-up the flanks making inspection difficult

Engineering Contradiction:
Improveinspection easeVSAvoidpackage structure
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The method applies local quality by creating wettable flank features only at specific locations where solderability and inspection are needed. Step cuts or dimples are formed on the side flanks to create localized geometric features that promote solder wicking, while the rest of the package structure remains unchanged. This localized modification enables solder to climb-up the flanks and form visible fillets for inspection, without adding complexity to the entire package structure.

Inventive Principle:
Principle #3Local quality

3Productivity

If multiple flat no-lead packages are manufactured together and singulated, then production efficiency is high, but good solder connections to lead lands on side flanks cannot be obtained

Engineering Contradiction:
Improveproduction efficiencyVSAvoidsolder connection quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The method performs preliminary plating of the side flanks while packages are still in array form on the conductive substrate, before singulation. This preliminary action ensures that all side flanks are pre-plated with solderable material while maintaining high production efficiency through batch processing. After plating, the array is singulated into individual packages, each retaining the plated side flanks for reliable solder connections.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method ensures full plating of side flanks, enhancing solderability and enabling effective automated optical inspection, with solder fillets forming on all sides, improving connection reliability and inspection ease.

Implementation Method 1

performing the process of electro-plating of the lead frame, thereby obtaining plating on the areas not covered by the conductive substrate

Methodology Applied
Scientific EffectElectro-plating: Electroplating

Data Source

PatentUS20260040956A1Method of fabricating a semiconductor integrated circuits package
Publication Date: 2026.02.05 NEXPERIA BV
  • US20260040956A1 patent drawing
  • US20260040956A1 patent drawing
  • US20260040956A1 patent drawing

AI summary

The present disclosure discloses a method of fabricating a semiconductor integrated circuits package with solder wettable plating and relates to a semiconductor package substrate with side wettable flank (SWF) features and a method of manufacturing thereof. In particular, the disclosure relates to leadless semiconductor devices and an associated method of manufacturing such devices. An object of the present disclosure is to provide a manufacturing technique allowing full plating of the side flanks by conventional electro-plating with an external conductive media.