Leadless Semiconductor Package with Coplanar Terminal Pads
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Solution Overview
Problem
High inductance in gull wing leads of surface mount semiconductor packages for high power and high frequency applications leads to system performance issues due to noise and inductance, and high temperature bonding processes can damage leadframes in leadless packages.
Innovation Solution
A leadless semiconductor device with a thick heat sink flange and pre-formed frame structure having bent terminal pads, where semiconductor dies are attached using a high temperature bonding process, and the structure is encapsulated with the terminal pads exposed to reduce inductance and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gull wing leads are used in surface mount semiconductor packages, then the package can be easily manufactured and assembled, but the inductance increases leading to noise and performance degradation in high frequency applications
Solution Approach 1:
The patent removes the traditional gull wing leads from the package structure entirely, replacing them with a leadless design where the terminal pads are directly exposed on the package bottom. This extraction of the problematic lead structure eliminates the source of inductance while maintaining manufacturing capability through standard encapsulation processes.
Solution Approach 2:
The invention transitions from a three-dimensional lead structure (gull wing leads extending outward) to a two-dimensional planar configuration where terminal pads lie flat on the package bottom surface. This dimensional change reduces the current path length and eliminates lead inductance, achieving lower inductance values suitable for high frequency applications.
2Strength
If high temperature bonding processes are used to attach semiconductor dies, then the bonding strength is improved, but the leadframe in leadless packages can be damaged
Solution Approach 1:
The patent removes the vulnerable leadframe structure from the package, eliminating the component that would be damaged by high temperature bonding processes. Without a leadframe to protect, the semiconductor die can be directly bonded to the substrate using high temperature processes to achieve maximum bonding strength without compromising structural integrity.
Solution Approach 2:
The invention uses a molded substrate that replicates the functional role of a leadframe (providing mechanical support and electrical connections) but with superior thermal and mechanical properties. This molded structure can withstand high temperature bonding processes that would damage traditional leadframes, enabling stronger die attachments.
3Reliability
If the package is fully encapsulated to protect internal components, then protection from external stresses is improved, but the terminal pads cannot be exposed for electrical connections
Solution Approach 1:
The patent applies selective encapsulation where the molding compound covers the internal components and bonding wires for protection, but deliberately leaves the terminal pad areas exposed. This local differentiation of encapsulation quality provides both protection for vulnerable internal structures and accessible connection points for electrical connections, resolving the contradiction between protection and operability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves lower package inductance, improved wire bond quality, and enhanced reliability for high power radiofrequency applications by maintaining flatness and coplanarity, resulting in improved system performance and reliability.
Implementation Method 1
a relatively thick heat sink flange... capable of dissipating, for example, greater than thirty watts of power
Implementation Method 2
heat sink flange... heat dissipating block
Data Source
Figure 1~3
Figure 4
Figure 5~6
AI summary
A packaged leadless semiconductor device (20) includes a heat sink flange (24) to which semiconductor dies (26) are coupled using a high temperature die attach process. The semiconductor device (20) further includes a frame structure (28) pre-formed with bent terminal pads (44). The frame structure (28) is combined with the flange (24) so that a lower surface (36) of the flange (24) and a lower section (54) of each terminal pad (44) are in coplanar alignment, and so that an upper section (52) of each terminal pad (44) overlies the flange (24). Interconnects (30) interconnect the die (26) with the upper section (52) of the terminal pad (44). An encapsulant (32) encases the frame structure (28), flange (24), die (26), and interconnects (30) with the lower section (54) of each terminal pad (44) and the lower surface (36) of the flange (24) remaining exposed from the encapsulant (32).