Leadless Semiconductor Package with Plated Interconnection Pads
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Solution Overview
Problem
Existing semiconductor packages, particularly quad flat no-lead (QFN) packages with matrix array packaging, face limitations in design flexibility and size reduction, as well as robustness for certain applications.
Innovation Solution
A method involving a metal base with a mask layer for forming interconnection and die attachment pads through plating, allowing for customizable pad placement and size, followed by encapsulation and cutting into discrete units, which enhances design flexibility and reduces package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional leadframe-based QFN packaging is used, then the package structure is simple and manufacturing is straightforward, but design flexibility for pad positioning is limited and package size cannot be reduced further
Solution Approach 1:
The invention extracts and removes the traditional leadframe structure from the package. Instead of using a pre-formed leadframe with fixed pad positions, the package directly mounts the semiconductor die to the substrate with interconnection pads formed on the substrate surface, eliminating the leadframe component entirely and enabling flexible pad positioning without structural constraints
Solution Approach 2:
The substrate serves multiple functions: it provides mechanical support for the semiconductor die, forms the interconnection pads directly on its surface, and enables flexible positioning of connection pads. This multi-functional substrate replaces the traditional leadframe's structural, electrical, and positioning roles, allowing customized pad configurations
2Volume of moving object
If traditional leadframe-based QFN packaging is used, then the manufacturing process is well-established, but package size and weight cannot be reduced
Solution Approach 1:
By removing the leadframe component entirely, the package volume is reduced as only the essential elements (substrate, die, encapsulation) remain. The elimination of the leadframe's physical structure directly enables smaller package dimensions while the manufacturing process adapts by forming pads directly on the substrate rather than attaching pre-formed leadframe pads
Solution Approach 2:
Instead of forming pads on a leadframe and then mounting the die, the invention inverts the sequence by first preparing the substrate with interconnection pads, then mounting the die directly to the substrate. This reversal eliminates the need for leadframe-based pad formation and enables more compact packaging
3Reliability
If traditional leadframe-based QFN packaging is used, then the package structure provides mechanical support, but robustness for certain end uses is insufficient
Solution Approach 1:
The invention uses composite material structures where the substrate and encapsulation material work together to provide enhanced mechanical support and robustness. The substrate provides a rigid mounting surface, while the encapsulation material provides structural protection and environmental sealing, creating a composite package structure that is more robust than traditional leadframe designs for certain applications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the creation of ultra-thin, small leadless semiconductor packages with improved design flexibility and robustness, allowing for customized pad configurations and reduced size, addressing limitations in existing QFN packages.
Implementation Method 1
plating layers of metal on the un-masked areas of the base to form the interconnection and die attachment pads
Data Source
AI summary
There is disclosed a method of making an electronic package (10) by: forming a metal base (50) on which to build the components of an electronic package; applying a mask layer (60) on the base to an area that is not to be occupied by interconnection pads (200) or die attachment pads (201) of the package; plating layers of metal on the un-masked areas of the base to form the interconnection and die attachment pads (200,201); removing the mask layer; mounting a semiconductor die (302) to at least one die attachment pad (201); electrically connecting the semiconductor die (302) to one or more interconnection pads (200); embedding the components on the base in an encapsulation material (300) to form a package; removing the metal base (50) to leave a package panel; and cutting the panel into discrete package units.