Leadless Semiconductor Device Side Wettable Flanks
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Solution Overview
Problem
Leadless packaged semiconductor devices pose challenges in inspecting solder joints due to hidden Input/Output terminals, making conventional Automated Optical Inspection (AOI) systems ineffective, and existing solutions like Automatic X-Ray Inspection (AXI) are expensive. Additionally, forming side pads for devices with specific I/O terminal arrangements is difficult using conventional electroplating processes.
Innovation Solution
The semiconductor device features four flat surfaces with two sides having full lead end height via electroless plating (ENIG or ENEPIG) and the other two sides with un-plated exposed Cu tie bars, allowing for side wettable flanks (SWFs) creation through chopper cuts and electroless plating, enabling full wettable lead end height and flat package surfaces, suitable for automotive industry standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional electroplating processes are used to form side pads, then manufacturing simplicity is maintained, but devices with specific I/O terminal arrangements (two separate functional dies with middle l/O terminals at one sidewall) cannot have side pads formed because the singulation cutting sequence electrically isolates the middle l/O terminals
Solution Approach 1:
The patent applies preliminary action by forming side pads on the lead frame structure before the final singulation cutting that would electrically isolate the middle l/O terminals. The manufacturing sequence is modified to: (1) form side pads on all l/O terminals including middle ones while they remain electrically connected, (2) then perform the singulation cuts. This preliminary formation of side pads before isolation resolves the contradiction by enabling side pad formation on devices with specific I/O arrangements that would otherwise be inmanufacturable.
2Measurement precision
If metal side pads are extended up the external sidewall of the device, then AOI inspection of solder joints becomes possible and device stability improves, but the manufacturing process becomes more complex due to additional plating and cutting steps
Solution Approach 1:
The patent applies dimensionality change by extending the side pads from the bottom surface upward along the external sidewalls of the device, creating a three-dimensional structure that provides both inspection capability and mechanical stability. The side pads wrap around the corners and extend up the sidewalls, allowing AOI systems to visually inspect solder joint quality from the side view, while the increased soldered area improves device stability and reduces tilting.
3Adaptability or versatility
If middle l/O terminals are located at one sidewall of the device on a lead frame structure, then device functionality is achieved, but side pads cannot be formed by conventional electroplating because the singulation cutting sequence electrically isolates these terminals
Solution Approach 1:
The patent resolves this contradiction by performing the side pad formation operation before the singulation cutting that would isolate the middle l/O terminals. The manufacturing sequence is specifically designed to: (1) apply electroplating to form side pads on all l/O terminals while they remain electrically connected through the lead frame, (2) then perform the singulation cuts that separate the device into individual packages. This preliminary action enables side pad formation on middle l/O terminals in devices with specific I/O arrangements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution facilitates effective AOI inspection of solder joints and enhances soldering quality, reducing tilting and improving shearing and bending performance, while meeting demanding automotive industry requirements by creating SWFs on leadless packages with thin lead frames, ensuring full compliance with AOI standards.
Implementation Method 1
two sides comprise a full lead end height with electroless plating
Data Source
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AI summary
This disclosure relates to a semiconductor device comprising four flat surfaces on four sides, wherein two sides comprise a full lead end height with electroless plating, and wherein other two sides comprise un-plated exposed Cu tie bar. The full lead end height with electroless plating is an ENIG plating or an ENEPIG plating.