Leadless Semiconductor Packaging Using Studs and Conductive Epoxy
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Solution Overview
Problem
Conventional semiconductor packages rely heavily on expensive and complex lead frames for electrical connections, which increase the bill of materials and processing complexity.
Innovation Solution
A lead-less packaged semiconductor device is created using conductive epoxy to affix a semiconductor die to a metal foil on a carrier substrate, with wire studs around the die for electrical connections, and encapsulant to define the package surfaces, eliminating the need for a lead frame. The method involves bonding studs onto the metal foil, wire bonding the die to the studs, encapsulating, and singulating the device, allowing for a ball grid array (BGA) package formation without traditional lead frames.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional lead frames are used for electrical connections, then reliable electrical connectivity is achieved, but the bill of materials cost and processing complexity increase
Solution Approach 1:
The patent extracts and removes the lead frame from the packaging structure, replacing it with wire bonds that directly connect the semiconductor die to external connection elements. This eliminates the complex lead frame geometry while maintaining electrical connectivity functions.
Solution Approach 2:
The patent applies different connection methods to different regions: wire bonds are used for internal die-to-stud connections, while solder balls or external terminals provide external connections. This localized approach replaces the uniform lead frame structure with specialized connection elements where needed.
2Reliability
If conventional lead frames are used for electrical connections, then electrical connectivity is maintained, but the bill of materials cost increases
Solution Approach 1:
The patent replaces the expensive, complex lead frame with simpler, less expensive materials such as wire bonds and basic substrates. The wire bonds use standard wire material, and the substrate can be a simple PCB or carrier, significantly reducing material costs while maintaining connectivity functionality.
Solution Approach 2:
The patent changes the material parameters from lead frame alloys to standard wire bond materials and substrate materials, which are generally less expensive and more readily available, thereby reducing the bill of materials cost.
3Reliability
If complex lead frame geometries are used, then electrical connections are achieved, but manufacturing complexity and processing difficulty increase
Solution Approach 1:
The patent segments the connection function into separate components: wire bonds for internal connections, substrates for mechanical support, and external terminals for external connections. This segmentation replaces the integrated but complex lead frame geometry with simpler, modular components that are easier to manufacture and assemble.
Solution Approach 2:
The patent replaces the mechanical lead frame structure with a combination of wire bonds (flexible electrical connections) and substrate-mounted terminals, simplifying the mechanical assembly process and reducing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the bill of materials and simplifies the packaging process by eliminating the need for complex lead frames, enabling cost-effective and efficient assembly of semiconductor devices with a lower material requirement and simplified processing.
Implementation Method 1
affixing a semiconductor die on the metal foil by a conductive epoxy
Implementation Method 2
wire bonding the semiconductor die to the plurality of studs
Implementation Method 3
encapsulating the semiconductor die, wire bonds, and studs with an encapsulant
Data Source
AI summary
Disclosed is a packaged semiconductor device having first and second major surfaces and comprising, a semiconductor die; conductive epoxy in contact with a surface of the semiconductor die, and exposed in a central region of the first major surface; a plurality of studs around a peripheral region of the first major surface; wire bonds between the semiconductor die and a surface of the studs which is remote from the first major surface, the wire bonds providing electrical connections between the semiconductor die and the plurality of studs; and encapsulant defining the second major surface and sidewalls of the packaged semiconductor device, wherein the first major surface is defined by the conductive epoxy, the encapsulant, and the studs.


