Leaf-Type Integrated Capacitor Parasitic Reduction
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Solution Overview
Problem
Integrated capacitors in semiconductor devices face challenges in reducing parasitic resistance and inductance while maintaining high capacitance density, which affects their performance in integrated circuit applications.
Innovation Solution
The development of integrated capacitors with a leaf-type structure that utilizes metal fingers with perpendicular offshoots and dielectric layers to improve parasitic performance by reducing parasitic resistance and inductance, while maintaining high capacitance density through specific structural arrangements and interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional capacitor structures are used, then manufacturing is simpler, but parasitic resistance and inductance are higher
Solution Approach 1:
The capacitor electrodes are segmented into multiple fingers that extend in opposite directions from a central axis. This segmentation reduces the loop area for current flow, thereby reducing parasitic inductance. The fingers are arranged in an interdigitated pattern with dielectric material between them, creating multiple capacitive elements in parallel that reduce equivalent series resistance while maintaining compact footprint.
Solution Approach 2:
The capacitor structure transitions from a planar configuration to a three-dimensional interdigitated arrangement with fingers extending in multiple directions (first and second opposite directions) from a central axis. This dimensional expansion allows for increased capacitance density and reduced parasitic elements by optimizing the electric field distribution in three-dimensional space rather than confined to a single plane.
2Productivity
If capacitor size is reduced to increase integration density, then more capacitors fit on chip, but parasitic resistance increases
Solution Approach 1:
The capacitor structure nests multiple functional elements within a compact footprint: central axis regions contain first electrodes, while peripheral regions contain second electrodes extending in opposite directions. Dielectric material is nested between the interdigitated fingers, creating multiple capacitive elements within a small area. This nested arrangement achieves high integration density while maintaining low parasitic resistance through the distributed finger configuration.
Solution Approach 2:
The interdigitated finger structure utilizes vertical stacking and multi-directional extension to increase effective capacitance area without proportionally increasing footprint. By arranging fingers in multiple layers and extending them in opposite directions from a central axis, the design achieves high capacitance density in a compact area while the distributed configuration reduces parasitic resistance compared to a single large electrode.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces parasitic resistance and inductance, enhancing the performance of integrated capacitors in terms of capacitance density and operating frequency, thereby improving overall circuit performance.
Implementation Method 1
a first conductive port, a second conductive port electrically isolated from and capacitively coupled to the first conductive port
Data Source
AI summary
A structure includes first, second, and third conductive leaf structures. The first conductive leaf structure includes a first conductive midrib and conductive veins. The second conductive leaf structure is electrically connected to the first conductive leaf structure, and includes a second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending away from the first conductive midrib. The third conductive leaf structure includes a third conductive midrib between the first conductive midrib and the second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending toward the second conductive midrib.