Leaf Clock Divider Layout to Cut Skew, Jitter, and Power
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Solution Overview
Problem
In programmable applications, distributing multiple clocking signals throughout a chip leads to increased power consumption and significant clock skew and jitter due to process, voltage, and temperature variations, especially when the clock source is far from the loads and the clocking signals are not known in advance.
Innovation Solution
Generating a related clocking signal at each leaf node from a single global clocking signal, reducing the need for multiple clock signals to be distributed and minimizing the impact of PVT variations, thereby reducing power consumption and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple clocking signals are distributed throughout the chip, then the clocking signals can reach various loads, but power consumption increases significantly
Solution Approach 1:
The system divides the clock distribution function into two segments: a single global clock signal is distributed throughout the chip to all leaf nodes, and then each leaf node locally generates its own related clocking signals. This segmentation eliminates the need to distribute multiple clock signals across the entire chip, reducing power consumption while ensuring reliable clock delivery to all loads.
Solution Approach 2:
The global clock signal acts as an intermediary that carries timing information to all leaf nodes without directly driving all loads. Each leaf node then uses this global clock signal to locally generate the specific clocking signals needed for its associated loads, reducing the overall power consumption of the clock distribution network.
2Reliability
If multiple clocking signals are routed throughout the chip, then various loads can be clocked, but clock skew between signals increases due to PVT variations
Solution Approach 1:
By segmenting the clock generation function to occur at each leaf node rather than at a centralized source, the patent ensures that each local clock signal experiences the same PVT variations as its corresponding global clock signal. This eliminates differential skew between multiple distributed clock signals, as each leaf node generates its signals locally from the same global reference.
Solution Approach 2:
Each leaf node generates its related clocking signals locally from the global clock signal received at that specific location. This local generation ensures that each clock signal pair (global and related) experiences identical PVT conditions at the leaf node, minimizing skew while allowing different parts of the chip to have different local clock characteristics.
3Reliability
If multiple clocking signals are distributed throughout the chip, then all loads can be clocked, but clock jitter between signals increases
Solution Approach 1:
The clock generation is segmented so that each leaf node independently generates its related clocking signals from the global clock signal. This ensures that jitter characteristics are consistent between the global and related signals at each leaf node, as they share the same signal path and PVT conditions, reducing differential jitter across the chip.
4Adaptability or versatility
If the clock source is positioned far from the loads, then chip layout is flexible, but power consumption and signal degradation increase
Solution Approach 1:
The clock distribution system is segmented into a centralized global clock source that only needs to reach leaf nodes (not all individual loads), and local clock generation at each leaf node. This allows the global clock source to be positioned flexibly while maintaining low power consumption, as it only drives signals to nearby leaf nodes rather than distributing multiple signals across the entire chip to all loads.
Data Source
AI summary
In some examples, a system includes a clock source, a clock distribution network, and a plurality of clock generators. The clock source is configured to generate a global clocking signal. The clock distribution network is configured to fan out the global clocking signal to a plurality of loads. The plurality of clock generators is configured to receive the global clocking signal through the clock distribution network. Each clock generator of the plurality of clock generators is configured to generate a related clocking signal to the global clocking signal from the received global clocking signal. Each clock generator of the plurality of clock generators maybe configured to supply the global clocking signal or the related clocking signal to its respective load of the plurality of loads.