Leakage-Biased Level Converter Circuit for Wide-Range Voltage Shifting
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Solution Overview
Problem
Conventional level converter designs for ultra-low power circuits face challenges in implementing robust and efficient wide-range level conversion due to contention between strong pull-up and weak pull-down devices, leading to high sensitivity to delay and power consumption.
Innovation Solution
The implementation of a leakage-biased synchronous level converter circuitry that uses NMOS leakage current to provide robust operation across a wide range of voltages and PVT variations, incorporating multiple MOS transistors and bypass control to support sub-threshold, near-threshold, and I/O voltages, and reduce switching power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional level converter designs are used for ultra-low power circuits, then level conversion between voltage domains is achieved, but switching power consumption is high due to contention between strong pull-up devices and weak pull-down devices
Solution Approach 1:
The patent employs dynamic sizing of transistors where the pull-up and pull-down devices are configured with different width-to-length ratios that adapt to the voltage conversion range. This dynamic configuration allows the circuit to maintain balanced drive strength across different voltage domains, reducing contention and switching power consumption while ensuring reliable operation.
Solution Approach 2:
The invention changes the electrical parameters of the transistor network by using multiple transistors with carefully selected threshold voltages and channel widths. By adjusting these parameters, the circuit achieves optimal power consumption characteristics across different voltage conversion scenarios while maintaining operation robustness against PVT variations.
2Reliability
If conventional level converter designs are used, then level conversion is achieved, but the circuit exhibits high sensitivity to delay and power variations
Solution Approach 1:
The patent merges multiple transistor devices into a unified level conversion network where pull-up and pull-down transistors are strategically connected. This merging creates a balanced structure that naturally compensates for delay variations and reduces sensitivity to process, voltage, and temperature changes without requiring additional complex control circuits.
Solution Approach 2:
The invention introduces intermediate voltage nodes and coupling structures that act as mediators between different voltage domains. These intermediary elements buffer the effects of delay and power variations, isolating the sensitivity issues from the main signal path and improving overall circuit robustness.
3Adaptability or versatility
If wide-range level conversion is implemented, then flexibility across voltage domains is achieved, but the circuit becomes more complex
Solution Approach 1:
The patent designs a universal level converter architecture that can handle multiple voltage conversion ranges using the same basic transistor network structure. By configuring the transistors with appropriate threshold voltages and using a standardized pull-up/pull-down arrangement, the circuit achieves wide-range adaptability without requiring separate dedicated circuits for each voltage domain.
Solution Approach 2:
The invention segments the voltage conversion function into distinct pull-up and pull-down transistor groups, each optimized for specific voltage ranges. This segmentation allows the circuit to achieve wide-range flexibility while keeping each segment relatively simple, avoiding the need for a monolithic complex structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables flexible and robust wide-range level conversion with reduced switching power consumption and improved energy efficiency across various voltage domains, supporting operation from 0.3V to 3.3V and 0.4V to 3.3V ranges, while maintaining robustness against PVT variations.
Implementation Method 1
By biasing circuitry using NMOS leakage current, the schemes and techniques described herein provide for robust operation across a wide range of low and high voltage supplies
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit. The integrated circuit may include clock circuitry having a first plurality of logic components arranged to receive a low voltage supply, a data input signal and a clock input signal and to provide a first plurality of intermediate signals and multiple intermediate clock signals. The integrated circuit may include level converter core circuitry having voltage biasing circuitry and voltage control circuitry arranged to receive a high voltage supply, the first plurality of intermediate signals and the multiple intermediate clock signals and to provide a second plurality of intermediate signals. The integrated circuit may include latch circuitry having a second plurality of logic components arranged to receive the high voltage supply, the low voltage supply and the second plurality of intermediate signals and to provide a data output signal.